J32562 Search Results

146R

Abstract: 146R-J 146R-W 41KD
Contextual Info: AT&T Data Sheet 146R Interrupt Holding Register Features • Up to four interrupt inputs per interrupt holding register ■ Cascadable inputs and outputs for expansion ■ Interfaced on either l/O-instructed or memorymapped basis ■ Convenient interface signals: AO, A1, E, IOR,

3055 7F

Abstract: j325 129CD
Contextual Info: AT&T i Data Sheet 129CD Quintuple Static Shift Register Features Vcc • Five 32-bit static shift registers ' 20 kß ■ 5.0 ± 0.5 V power supply: 250 mW max ■ TTL-com patible input/output ■ Single-phase clock, positive-edge triggered INPUT AND CLOCK PINS '

DS1E

Abstract: DS-873
Contextual Info: 630AJ R eceive C o n v e rte r » Features • Data lo o p b a ck mode ■ Internal phase-locked loop ■ A utom atic o u tp u t shutdow n ■ U n ipolar clo ck o utp ut ■ D ual-rail PCM o u tp u t ■ TTL-com patible o utput Description The 630AJ Receive Converter hybrid integrated circu it HIC extracts clo ck and PCM inform ation

YD 8287

Abstract: we32100
Contextual Info: Data Sheet T7110 Synchronous Protocol Data Formatter with Serial Interface Features Host Interface Features • Compatible with AT&T’s WE 32100 Microprocessor and with Intel’s iAPX86 and Motorola’s MC68000 microprocessor series ■ On-chip 16-channel DMA memory address

DSP16A

Abstract: WE DSP16A dsp16a user guide we dsp32 at&t dsp dsp32c G010343 XWXX "saturation value" xlxxx
Contextual Info: A T & T HELEC I C bME D • D D S D O S b D D 1 0 32 7 77^ M A T T E INTRODUCTION Architecture 1. INTRODUCTION The WE DSP16A Digital Signal Processor is a 16-bit, high-performance, CMOS integrated circuit. This device can be programmed to perform a wide variety of signal-processing functions. This is the DSP

Contextual Info: AT&T Product Announcement ATE-Series Digital Bipolar G ate Arrays AT&T Microelectronics is introducing a new series to the family of existing custom gate arrays. The customized high-speed TTL-ECL gate arrays are designed using Scaled-Fast OxideIsolated Logic SFOXIL bipolar

ic 555 timer IR remote control TRANSMITTER AND RE

Abstract: T7100A-BC
Contextual Info: T7100A X.25 Protocol Controller Features • 5-M Hz clock max ■ Triple-channel DMA with standard interface ■ 250-kb/s serial data rate (max) ■ Programmable retransmission counter (N2) ■ 8-bit data bus ■ Password exchange mechanism for dial-up operation

LS259

Abstract: TPD10-TPD9 DS8815
Contextual Info: AT&T Preliminary Data Sheet T7200 Multi-Port Repeater Unit Controller Features Functionally conforms to IEEE 802.3 CSMA/CD specifications 12-port repeater: 11 twisted-pair, 1 AUI Automatic preamble generation APG to minimize bit loss Manchester encoding of transmitted data

KD 502

Abstract: 146R 41KD 41KD-J 41KD-W ATT 41kd
Contextual Info: 41 K D Interrupt Holding R e gister Features • Up to four interrupt inputs per interrupt holding register Masking and interrupt registers may be read or written to verify operational integrity ■ Cascadable inputs and outputs for expansion TTL/CMOS-compatible

Contextual Info: fpAfcT Data Sheet 146R Interrupt Holding R egister Features • Up to four interrupt inputs per interrupt holding register ■ Cascadable inputs and outputs for expansion ■ Interfaced on either l/O-instructed or memorymapped basis ■ Convenient interface signals: AO, A1, E, IOR,

define RELAY DRIVER

Abstract: relay CMOS technology sn75437
Contextual Info: LC1107AC Quad Relay/Peripheral Driver Features • Standard +5 V supply operation ■ High current capability: 150 mA per driver, 600 mA total ■ Built-in flyback protection for inductive loads ■ Outputs can be tied together for increased current capability

DSP3210

Abstract: DSP32C AT&T dsp32 DSP32 Floating-Point Arithmetic at&t dsp dsp32 att 3d graphics IS3938 motorola idp
Contextual Info: A T & T MELEC I C b4E » • 005002b DDlDflME STT ■ ATT2 DSP3210 Information Manual Introduction 1. INTRODUCTION The AT&T DSP3210 brings the power of floating-point signal processing to personal computers and workstations opening a wide range of multimedia applications. From its conception, the DSP3210 has been engineered with a

Contextual Info: AT&T Data Sheet T7260 and T7261 ISDN U-lnterface Basic Access Transceiver Chip Set Features • U -interface fo r 2-wire operation ■ Pin-selectable fo r central office CO sw itch and netw ork term ination (NT) a pp lica tio n s ■ A daptive equalization and a utom atic gain

we32100

Abstract: 0TE15
Contextual Info: Data Sheet T7102A-X.25/X.75 Protocol Controller Features • 24-bit address bus to address a 16-Mbyte address space ■ Independently programmable transmit and receive window size ■ Dual-channel DMA with standard interface, including DMA request, DMA acknowledge,

Contextual Info: T7001 Random Number Generator Features On-chip or external high-frequency oscillator source option On-chip or external jitter oscillator source option Data ready and alarm output flags readable from the data bus or independent output pins, allowing either processor interrupt or

LS373

Abstract: 41KP LS164 ATT 41 fukoku
Contextual Info: AT&T Data Sheet 41 KP L atch ed S erial R eg ister Benefits Synchronous data transfers • Combines functions of the LS373 and LS164 devices on a single chip Useful as input or output port for microprocessors ■ Cost and space saving TTL and CMOS compatible

j325

Abstract: eel -16-2005 3055 7F ATE1000 ATE3000 ATE6000 ttl buffer ATT Microelectronics
Contextual Info: Product Announcement ! AT&T ATE-Series D igital Bipolar G ate Arrays AT&T Microelectronics is introducing a new series to the family of existing custom gate arrays. The customized high-speed TTL-ECL gate arrays are designed using Scaled-Fast OxideIsolated Logic SFOXIL bipolar

Contextual Info: 41LF Quad Differential Line Receiver Features • Pin-equivalent to the general-trade AM26LS32 device, with improved speed and reduced power consumption ■ Four line receivers per package ■ Meets ESDI Standards ■ Complementary inputs for each line receiver

KD 502

Abstract: KD 3055 146R 41KD 41KD-J 41KD-W ATT Microelectronics
Contextual Info: i Data Sheet AT&T 4 1 KD In terru p t Holding R eg ister Features Up to four interrupt inputs per interrupt holding register Masking and interrupt registers may be read or written to verify operational integrity Cascadable inputs and outputs for expansion

DSP3210

Abstract: DSP32C
Contextual Info: A T & T MELEC I C b4E » • 005002b DDlDflME STT ■ ATT2 DSP3210 Information Manual Introduction 1. INTRODUCTION The AT&T DSP3210 brings the power of floating-point signal processing to personal computers and workstations opening a wide range of multimedia applications. From its conception, the DSP3210 has been engineered with a

DS-873

Contextual Info: AT&T Data Sheet 129CD Q uintuple S tatic Shift R egister vcc Features • Five 32-bit static shift registers • 20 kfi ■ 5.0 ± 0.5 V power supply: 250 mW max ■ TTL-compatible input/output ■ Single-phase clock, positive-edge triggered INPUT AND CLOCK PINS '

Contextual Info: Advance Data Sheet WE DSP16A Digital Signal Processor Description The WE DSP16A Digital Signal Processor is a 16-bit high-speed programmable integrated circuit. The device is fabricated in low-power CMOS technology and is packaged in an 84pin plastic leaded chip carrier. The DSP16A

Contextual Info: \ '• AKT Data Sheet T7000A Digital Encryption Processor Features ■ Programmable DES ciphering modes q Electronic codebook ECB o Cipher block chaining (CBC) a 1-, 8-, or 64-bit cipher feedback (CFB) ° Output feedback (OFB) ■ Ciphering rates of 235,000 operations/s for

Contextual Info: AT&T Preliminary Data Sheet ATE2000 Series Gate Array Description The ATE2000 High-Speed Gate Array is a member of the customized TTL-ECL gate array family and is designed using advanced Scaled Fast Oxide Isolated Logic SFOXIL Bipolar technology. The device