T74LS10 Search Results

Contextual Info: £ jJ S G S - T H O M S O N T74LS109A H J O T M IiM g i DUAL JK PO SITIVE E D G E-TR IG G E R E D FLIP-FLOP DESCRIPTIO N The T74LS109A consist of two high speed com­ pletely independent transition clocked JK flip-flops. The docking operation is independent of rise and fall

T74LS10B1

Contextual Info: SES Î0 TRIPLE 3-INPUT NAND GATE DESCRIPTION The T54LS10/T74LS10 is a high speed TRIPLE 3-INPUT NAND GATE fabricated in LOW POWER SCHOTTKY technology. 1 B1 Plastic Package D1/D2 Ceramic Package M1 Micro Package C1 Plastic Chip Carrier ORDERING NUMBERS: T54LS10 D2

connecting diagram for ic 74 08

Abstract: H2635
Contextual Info: DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS109-109A consist of two high sjjeed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operatioji as a D flip-flop by simply

T54LS107AD2

Contextual Info: PRELIMINARY DATA DUAL JK FLIP-FLOP DESCRIPTION The T54LS107A/T74LS107A is a Dual JK flip-flop with individual J, K, clock pulse and direct Reset inputs. The HIGH-to-LOW transition of the clock ini­ tiates output changes. A LOW signal on CD input overrides the other inputs and makes the Q out­

T74LS244

Abstract: T74LS5 t74LS161a sgs T74LS293 T74LS02
Contextual Info: ALPHANUMERICAL INDEX I Type Number T74LS00 T74LS01 T74LS02 T74LS03 T74LS04 T74LS05 T74LS08 T74LS09 T74LS10 T74LS11 T74LS12 T74LS13 T74LS14 T74LS15 T74LS20 T74LS21 T74LS22 T74LS26 T74LS27 T74LS28 T74LS30 T74LS32 T74LS33 T74LS37 T74LS38 T74LS40 T74LS42 T74LS51

Contextual Info: SG S-THO IA SO N T74LS10 TRIPLE 3-INPUT NAND GATE D ES C R IPT IO N The T74LS10 is a high speed TRIPLE 3-INPUT NAND GATE fabricated in LOW POWER SCHOTTKY technology. B1 D1 P la s tic P a ckage (C e ra m ic P a ckage) M1 C1 (M ic ro P a ckage) (P la s tic C h ip C a rrier)

165-V4

Abstract: 185ra
Contextual Info: S G S-THOHSON D7E D I 7 ^ 2 3 7 0Qlt,020 S C 16148 D r-4&~ J 7-¿>7 LOW POWER SGHOTTKY T54LS107A T74LS107A INTEGRATED • CIRCUITS PRELIMINARY DATA DUAL JK FLIP-FLOP DESCRIPTION The T54LS107A/T74LS107A is a Dual JK flip-flop with individual J, K, clock pulse and direct Reset

Contextual Info: as DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS109-109A consist of two high sg>eed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK

T74LS10B1

Abstract: T54LS10D2 T74LS10
Contextual Info: TRIPLE 3-INPUT NAND GATE Î0 DESCRIPTION The T54LS10/T74LS10 is a high speed TRIPLE 3-INPUT NAND GATE fabricated in LOW POWER SCH OTTKY technology. B1 Plastic Package D1/D2 Ceramic Package M1 Micro Package C1 Plastic Chip Carrier ORDERING NUMBERS: T54LS10 D2

T0606

Contextual Info: S G S-THOHSÔN D7E D | 7 ^ 2 3 7 Mlfc.053 0 | LOW POWER SCHOTTKY INTEGRATED CIRCUITS '* - i 16151 D 7 ~ -V < £ -^ 7 -a 7 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS109-109A consist of two high s£eed completely independent transition clocked

TDA0161 equivalent

Abstract: 1N3393 BDX54F equivalent byt301000 bux transient voltage suppressor ST90R9 ua776mh sgs 2n3055 Transistor morocco mje13007 inmos transputer reference manual
Contextual Info: SHORTFORM 1995 NOVEMBER 1994 USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein:

t74ls157

Abstract: 74LS00 fan out 74LS00E T74LS74 74LS00 QUAD 2-INPUT NAND GATE 74LS00 74LS00 nand gate NAND 74LS00 74ls00 series T74LS367
Contextual Info: LOW POWER SCHOTTKY TTL-54/74 LS SERIES DESIGN CO NSIDERATIO NS SUPPLY VOLTAGE — +5V ±10% +5V ±5% T54 SERIES T74 SERIES NOISE MARGIN — V il 0.7V, V il 0.8V, 2.0V, 2 .0 V, V ih V ih Vol Vol 0.4V, V o h 2.5V 0.5V, V oh 2.7V T 5 4 SERIES T 7 4 SERIES INPUT LOADING —