T74LS11 Search Results

WCL 209

Abstract: ltzt
Contextual Info: as DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS114/114A offer common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are de­ signed so that when the clock goes HIGH, the in­ puts are enabled and data will be accepted. The

Contextual Info: S G S-THOMSON 42E D 0033340 SCS-THO M SO Ü 3 ISûTH T -y é - O T - o i T7 4 L S 114A [R{tlD i ê [l[LIl(g?^(s)[î!!lD(gi DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP D E S C R IP T IO N The T74LS114A offer common clock and common clear Inputs and Individual J, K, and set inputs. The­

Contextual Info: SGS-THOMSON r - v s - i s T74LS11 TRIPLE 3 INPUT AND GATE D E S C R IP T IO N The T74LS11 is a high speed TRIPLE 3-INPUT AND G ATE fabricated in LOW PO W ER SCHOTTKY technology. S C H E M A T IC B1 Plastic Package D I' (Ceramic Package) M1 (Micro Package)

Contextual Info: ss DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP $0^ DESCRIPTION The T54LS/T74LS113/113A offers individual J, K, set and clock inputs. These monolithic dual flipflops are designed so that when the clock goes HIGH, the inputs are enabled and data will be ac­ cepted. The logic level of the J and K may be allo­

T74LS244

Abstract: T74LS5 t74LS161a sgs T74LS293 T74LS02
Contextual Info: ALPHANUMERICAL INDEX I Type Number T74LS00 T74LS01 T74LS02 T74LS03 T74LS04 T74LS05 T74LS08 T74LS09 T74LS10 T74LS11 T74LS12 T74LS13 T74LS14 T74LS15 T74LS20 T74LS21 T74LS22 T74LS26 T74LS27 T74LS28 T74LS30 T74LS32 T74LS33 T74LS37 T74LS38 T74LS40 T74LS42 T74LS51

Contextual Info: rrz SGS-THOMSON T74LS11 TRIPLE 3-INPUT AND GATE DESCRIPTION The T74LS11 is a high speed TRIPLE 3-INPUT AND GATE fabricated in LOW POWER SCHOTTKY technology. D1 B1 Plastic Package (Ceramic Package) M1 C1 (Micro Package) (Plastic Chip Carrier) ORDER CODES :

t114a

Abstract: 1t4a T54LS/T74LS114/114A
Contextual Info: S G K ? C m Î i S-THOnSON $ 1 ÎM 07E M D | 7^5^53? 0 UJi hü 31 4 | LOW POWER SCHOTTKY INTEGRATED CIRCUITS i l Ì T 7 4 L S t1 4 |M 67C 1 6 1 6 7 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS114/114A offer common clock and common clear inputs and individual J, K, and

T74LS11B1

Abstract: T54LS11D2 T74LS11
Contextual Info: as ü .-WÊÊÊÊHÊÊÊir*' TRIPLE 3-INPUT AND GATE DESCRIPTION The T54LS11/T74LS11 is a high speed TRIPLE 3-INPUT AND GATE fabricated in LOW POWER SCH OTTKY technology. i B1 D1/D2 Plastic Package Ceramic Package & M1 C1 Plastic Chip Carrier Micro Package

Contextual Info: f Z 7 S C S -T H O M S O N # & T 7 4 L S 1 12 A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T74LS112A is a dual JK flip-flop featuring in­ dividual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH,

Contextual Info: s G 0 ?E S -T H O n S O N D | 7 ^ 5 ^ 3 7 D 01b 033 3 | LOW POWER SCHOTTKY i T54LSÌ13/113^ T74LS113/113A INTEGRATED CIRCUITS 67C 1 6 1 6 1 D T -*& -o 7 -o 7 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTIO N The T54LS/T74LS113 /1 13A offers individual J, K,

T74LS11B1

Abstract: T74LS11
Contextual Info: as ü .-W ÊÊÊÊH ÊÊÊir* * ' TRIPLE 3-INPUT AND GATE DESCRIPTION The T54LS11/T74LS11 is a high speed TRIPLE 3-INPUT AND GATE fabricated in LOW POWER SCH OTTKY technology. i B1 D1/D2 Plastic Package Ceramic Package & M1 C1 Plastic Chip Carrier Micro Package

Contextual Info: M SS DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS112A is a dual JK flip-flop fea­ turing individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will

T74LS112AB1

Abstract: T54LS112AD2 n70v
Contextual Info: DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS112A is a dual JK flip-flop fea­ turing individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K may

Contextual Info: £ ÿ j S C S -T H O M S O N L ìO T q * ì T74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP D E S C R IP T IO N The T74LS114A offer common clock and common clear inputs and individual J, K, and set inputs. The­ se monolithic dual flip-flops are designed so that

LC-D023

Contextual Info: DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS113/113A offers individual J, K, set and clock inputs. These monolithic dual flip­ flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be ac­ cepted. The logic level of the J and K may be allo­

T74LS

Contextual Info: SCS-THOMSON [iJ g ïïl P u S T 7 4 L S 1 13 A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T74LS113A offers individual J, K, set and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are

TDA0161 equivalent

Abstract: 1N3393 BDX54F equivalent byt301000 bux transient voltage suppressor ST90R9 ua776mh sgs 2n3055 Transistor morocco mje13007 inmos transputer reference manual
Contextual Info: SHORTFORM 1995 NOVEMBER 1994 USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein:

t74ls157

Abstract: 74LS00 fan out 74LS00E T74LS74 74LS00 QUAD 2-INPUT NAND GATE 74LS00 74LS00 nand gate NAND 74LS00 74ls00 series T74LS367
Contextual Info: LOW POWER SCHOTTKY TTL-54/74 LS SERIES DESIGN CO NSIDERATIO NS SUPPLY VOLTAGE — +5V ±10% +5V ±5% T54 SERIES T74 SERIES NOISE MARGIN — V il 0.7V, V il 0.8V, 2.0V, 2 .0 V, V ih V ih Vol Vol 0.4V, V o h 2.5V 0.5V, V oh 2.7V T 5 4 SERIES T 7 4 SERIES INPUT LOADING —