A0LA Search Results

C-165-5101-500

Abstract: C1655 A0LA
Contextual Info: TABLE 1 TABLE ± 11 DRW NO. ZONE REV SCR NO. DESCRIPTION DSMH-6BUQKA.VER01 PART REV NUMBER DESCRIPTION N U M B E R OF WAFERS A B C 10 18.50 9 16.65 25 46.25 24 44.40 NEW MLEE-6K9H3D.VER01 CHANGED A0LA-7KMSHR.VER01 165-5101-735 A 165-5101-769 A 30/Li 30m IN.

Shared resource arbitration

Contextual Info: miMHS PRELIMINARY March 1994 L 67005 DATA SHEET 8 KX 8 CMOS DUAL PORT RAM 3.3 VOLT FEATURES VERSATILE PIN SELECT FOR MASTER OR SLAVE: - M/S= H FOR BUSY OUTPUT FLAG ON MASTER - M/S = L FOR BUSY INPUT FLAG ON SLAVE INT FLAG FOR PORT TO PORT COMMUNICATION FULL HARDWARE SUPPORT OF SEMAPHORE

Contextual Info: HIGH-SPEED 36K 4K x 9-BIT SYNCHRONOUS DUAL-PORT RAM PRELIMINARY IDT70914S Integ ra te d D evice Technology, Inc. FEATURES: DESCRIPTION: • High-speed clock-to-data output times — Military: 20/25ns (max.) — Commercial: 15/20/25ns (max.) • Low-power operation

Contextual Info: HIGH-SPEED 16Kx 8 DUAL-PORT STATIC RAM IDT7006S/L Integrated Device Technology, Inc. M/S = L for BUSY input on Slave • Interrupt Flag • On-chip port arbitration logic • Full on-chip hardware support of semaphore signaling between ports • Fully asynchronous operation from either port

Contextual Info: |9 | N a HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM w Éy IDT7005S/L Integrated Device Technology, Inc. • Interrupt Flag • On-chlp port arbitration logic • Full on-chip hardware support of semaphore signaling between ports • Fully asynchronous operation from either port

Contextual Info: HIGH-SPEED 3.3V 16Kx 16 DUAL-PORT STATIC RAM PRELIMINARY IDT70V261S/L Integrated Device Technology, Inc. FEATURES: • M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave • Interrupt Flag • Devices are capable of withstanding greater than 2001V

Contextual Info: IDT7130SA/LA IDT7140SA/LA CMOS DUAL-PORT RAM 8K 1Kx 8-BIT Integrated Device Technology, Inc. FEATURES DESCRIPTION • High-speed access — Military: 25/35/55/100ns (max.) —Commercial: 25/35/55/100ns (max.) —Commercial: 20ns 7130 inPLCC and TQFP • Low-power operation

Contextual Info: PRELIMINARY IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM Integrated Device Technology, Inc. • M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave • Interrupt Flag • Devices are capable of withstanding greater than 2001V

Contextual Info: CMOS DUAL-PORT RAM 8 K 1 K x 8-BIT IDT7130SA/LA IDT7140SA/LA Integrated Device Technology, Inc. FEATURES DESCRIPTION • High-speed access — Military: 2 5 /3 5 /5 5 /1 00ns (max.) — Commercial: 2 5 /3 5 /5 5 /1 00ns (m ax.) — Commercial: 20ns in P LC C only for 7130

Contextual Info: HIGH-SPEED 8K x 9 DUAL-PORT M J IDT7015S/L STATIC RAM Integrated Device Technology, Inc. FEATURES: • True Dual-Ported memory cells which allow simulta­ neous reads of the same memory location • High-speed access — Military: 20/25/35ns max. — Commercial: 12/15/17/20/25/35ns (max.)

dt7130

Contextual Info: INTEGRATE» DEVICE k& E D • MÖ25771 GGia^? SSb ■ IDT IDT7130SA/LA IDT7140SA/LA C M O S D U A L -P O R T RAM 8K 1K x 8-B IT Integrated Device Technology, Inc. FEATURES DESCRIPTION • High-speed access — Military: 25/35/55/100ns (max.) — Commercial: 25/35/55/100ns (max.)

Contextual Info: HIGH-SPEED 3.3V 16Kx 16 DUAL-PORT STATIC RAM PRELIMINARY IDT70V26S/L Integrated Device Technology, Inc. • FEATURES: • • • • • True Dual-Ported m em ory cells which allow sim ulta­ neous reads of the same m em ory location High-speed access — Com mercial: 25/35/55ns max.

Contextual Info: IDT7130SA/LA 1DT7140SA/LA CMOS DUAL-PORT RAM 8 K 1 K x 8-BIT Integrated Device Technology, Inc. FEATURES DESCRIPTION • High-speed access — Military: 25/30/35/45/55/70/90/100/120ns (max.) —Commercial: 20/25/30/35/45/55/70/90/100ns (max.) • Low-power operation

Contextual Info: Integrated Device Technology, Inc. HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM more than one device M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling

Contextual Info: HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM IDT7005S/L In te g ra te d D e v ic e T ec h nology, In c . FEATURES: • Interrupt Flag • On-chip port arbitration logic • Full on-chip hardware support of semaphore signaling between ports • Fully asynchronous operation from either port

025X

Abstract: A12L IDT7025 IDT7025L IDT7025S A0L-A12L
Contextual Info: HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Military: 20/25/35/55/70ns max. – Industrial: 55ns (max.) – Commercial: 15/17/20/25/35/55ns (max.)

sem 3040

Abstract: DSC-3040 A12L A13L IDT70V261 IDT70V261L IDT70V261S IDT70V261PF
Contextual Info: HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 25/35/55ns max. Low-power operation – IDT70V261S Active: 300mW (typ.)

sem 3040

Abstract: DSC-3040 A12L A13L IDT70V261 IDT70V261L IDT70V261S 70V261L
Contextual Info: PRELIMINARY IDT70V261S/L HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM Integrated Device Technology, Inc. FEATURES: • True Dual-Ported memory cells which allow simultaneous access of the same memory location • High-speed access — Commercial: 25/35/55ns max.

Contextual Info: S March 1994 DATA SHEET_ M 67130/ M 67140 h im R M 1Kx 8 CMOS DUAL PORT RAM FEATURES . . . . FAST ACCESS TIME 35 NS TO 55 NS 30 NS PRELIMINARY FOR COMMERCIAL ONLY . 67130L/67140L LOW POWER 67130W67140V VERY LOW POWER . EXPANDABLE DATA BUS T 0 16 BITS OR MORE

IDT7024

Abstract: IDT7024L IDT7024S
Contextual Info: IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM Integrated Device Technology, Inc. more than one device • M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave • Busy and Interrupt Flags • On-chip port arbitration logic • Full on-chip hardware support of semaphore signaling

Contextual Info: PRELIMINARY SEMCONDUCTOR CY7B138 CY7B139 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features Functional Description • 0.8-micron BiCMOS for high per­ formance • High-speed access — 15 ns com’l — 25 ns (mil) • Automatic power-down • Fully asynchronous operation

2746 transistor

Abstract: IDT7133 IDT7143 J68 10A K 2746
Contextual Info: IDT7133SA/LA IDT7143SA/LA HIGH SPEED 2K X 16 DUAL-PORT SRAM Features ◆ ◆ ◆ ◆ ◆ ◆ High-speed access – Military: 25/35/45/55/70/90ns max. – Industrial: 25/35/55ns (max.) – Commercial: 20/25/35/45/55/70/90ns (max.) Low-power operation – IDT7133/43SA

idt7132

Abstract: 71421
Contextual Info: IDT71321SA/LA HIGH SPEED IDT71421SA/LA 2K X 8 DUAL-PORT STATIC RAM WITH INTERRUPTS Features ◆ ◆ ◆ ◆ High-speed access – Commercial: 20/25/35/55ns max. – Industrial: 55ns (max.) Low-power operation – IDT71321/IDT71421SA — Active: 325mW (typ.)

256K DPRAM

Abstract: IDT70914 IDT709149 70V261 70V25 70V24
Contextual Info: SYNCHRONOUS DUAL-PORT STATIC RAMS FOR DSP AND COMMUNICATION APPLICATIONS APPLICATION NOTE AN-144 Integrated Device Technology, Inc. By Jeffrey C. Smith ABSTRACT The Sequential Access Random Access Memory The first of the synchronous components to be presented