A12R Search Results

Contextual Info: LED Assy. No. Peak Wave Length p nm Emitted Color Lens Appearance Electro-Optical Data @ 20mA Vf Iv (VDC) (mcd) TYP TYP Viewing Angle PM5-A12R12V 660 RED RED DIFFUSED 12 39 120 PM5-A12Y12V 585 YELLOW YELLOW DIFFUSED 12 87 120 PM5-A12G12V 525 GREEN GREEN DIFFUSED

Contextual Info: LED Assy. No. Peak Wave Length λp nm Emitted Color Lens Appearance Electro-Optical Data @ 20mA Vf Iv (VDC) (mcd) TYP TYP Viewing Angle PM5-A12R12V 660 RED RED DIFFUSED 12 39 120 PM5-A12Y12V 585 YELLOW YELLOW DIFFUSED 12 87 120 PM5-A12G12V 525 GREEN GREEN DIFFUSED

A16HR

Abstract: A15R a12r appa a12 appa A16R appa 76 appa a16
Contextual Info: КЛЕЩИ ТОКОИЗМЕРИТЕЛЬНЫЕ APPA A10 серия Токоизмерительные клещи A16HR, A16R, A16, A15R, A15, A12R, A12, A11R, A11 I I True RMS * U U R f I I I * True RMS * U U R True RMS U U R f f APPA A16HR Днём и ночью В ы с о к о к о н т р а с т н ы й

Contextual Info: TOSHIBA TC5164 5 805AJ/AFT/AJS/AFTS-40,-50 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 8,388,6O8-WORD X8-BIT EDO (HYPER PAGE) DYNAMIC RAM DESCRIPTION The TC5164(5)805AJ/AFT/AJS/AFTS is an EDO (hyper page) dynamic RAM organized as 8,388,608

9l reset

Abstract: CY7C0852V-133AC CY7C09289V CY7C09369V CY7C09379V
Contextual Info: CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Features Functional Description

IDT709079

Abstract: IDT709089
Contextual Info: 025/0251 CY7C09079/89/99 CY7C09179/89/99 PRELIMINARY 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 6 Flow-Through/Pipelined devices — 32K x 8/9 organizations CY7C09079/179

Shared resource arbitration

Contextual Info: miMHS PRELIMINARY March 1994 L 67005 DATA SHEET 8 KX 8 CMOS DUAL PORT RAM 3.3 VOLT FEATURES VERSATILE PIN SELECT FOR MASTER OR SLAVE: - M/S= H FOR BUSY OUTPUT FLAG ON MASTER - M/S = L FOR BUSY INPUT FLAG ON SLAVE INT FLAG FOR PORT TO PORT COMMUNICATION FULL HARDWARE SUPPORT OF SEMAPHORE

IDT709269

Abstract: IDT709279 014L 100-PIN
Contextual Info: fax id: 5217 CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY ^ C Y P R E S S ~ 16K/32K/64K x16/18 Synchronous Dual Port Static RAM Features Low o p e ratin g p ow er • True D u al-P o rted m e m o ry cells w h ich allo w sim u lta­ n eo us ac c e s s o f th e s a m e m e m o ry location

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Abstract: TNC 24 mk 2 026R CY7C09569V tb136 A14L CY7C09579V
Contextual Info: «oaHaoooiMMMWfMMMMMM!9:^ v’*'» -• -■ -■ -^ jjÉBT *¿f5’00“’ '*'^ 7“T ■ ■ ■ ■ <1; .r {• o CY7C09569V CY7C09579V PRELIMINARY f:,ò b 3.3V 16K/32K x 36 FLEx36 Synchronous Dual-Port Static RAM • 3.3V Low o p e ratin g p ow er

Contextual Info: HIGH-SPEED 3.3V 8 K x 16 DUAL-PORT STATIC RAM IDT70V25S/L In te g ra te d D e v iz e T e c h n o lo g y , l i e . FEATURES: • True Dual-Ported m em ory cells which allow sim ulta­ neous reads of the sam e m em ory location • H igh-speed access — Com m ercial: 25/35/55ns max.

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Contextual Info: HIGH-SPEED 32K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT709279S/L I n t e g r a te d D e v iz e T e c h n o lo g y , l i e . FEATURES: Full synchronous operation on both ports - 4ns setup to clock and 1 ns hold on all control, data, and address inputs

Contextual Info: HIGH-SPEED 8K x 9 DUAL-PORT IDT7015S/L STATIC RAM I n t e g r a t e d D e v iz e T e c h n o lo g y , l i e . FEATURES: • True Dual-Ported m em ory cells which allow sim ulta­ neous reads of the sam e m em ory location • H igh-speed access — M ilitary: 20/25/35ns max.

Contextual Info: dt | ; HIGH-SPEED 16Kx 8 DUAL-PORT STATIC RAM IDT7006S/L In te g ra te d De v ic e T e ch n o lo g y, Inc. FEATURES: • • • True Dual-Ported m em ory cells w hich allow sim ulta­ neous access of the sam e m em ory location • H igh-speed access — M ilitary: 20/25/35/55/70ns max.)

Contextual Info: PRELIMINARY IDT70V27S/L HIGH-SPEED 3.3V 32Kx 16 DUAL-PORT STATIC RAM In te g ra te d D e v iz e T e c h n o lo g y , l i e . FEATURES: • IDT70V27 easily expands data bus w idth to 32 bits or more using the M aster/Slave select when cascading more than one device

Contextual Info: |9 | N a HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM w Éy IDT7005S/L Integrated Device Technology, Inc. • Interrupt Flag • On-chlp port arbitration logic • Full on-chip hardware support of semaphore signaling between ports • Fully asynchronous operation from either port

Contextual Info: HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM ydt IDT7015S/L Integrated De^/ice Technology, Inc. FEATURES: • True Dual-Ported m em ory cells w hich allow sim ulta­ neous access of the sam e m em ory location • H igh-speed access — M ilitary: 20/25/35ns max.)

Contextual Info: HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM IDT7008S/L F eatu res * * * True Dual-Ported m em ory cells w hich allow sim ultaneous more u sin g the Master/Slave select when ca sca d in g more High-speed a c c e ss than one device_ - M ilitary: 25/35/55ns max.

Contextual Info: HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM IDT7015S/L FEATURES: * * True Dual-Ported memory cells which allow simultaneous reads of the sam e memory location * * * B u sy and Interrupt Flag - Military:20/25/35ns max. * On-chip port arbitration logic - Commercial: 12/15/17120125135ns (max.)

Contextual Info: HIGH-SPEED 3.3V 32K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS PRELIMINARY IDT70V7278S/L Features 32K x 16 Bank-Switchable Dual-Ported SRAM Architecture * processor communications; interrupt option Interrupt flags with programmable masking

Contextual Info: HIGH-SPEED 8K x 9 DUAL-PORT M J IDT7015S/L STATIC RAM Integrated Device Technology, Inc. FEATURES: • True Dual-Ported memory cells which allow simulta­ neous reads of the same memory location • High-speed access — Military: 20/25/35ns max. — Commercial: 12/15/17/20/25/35ns (max.)

Contextual Info: PRELIMINARY IDT70V27S/L HIGH-SPEED 3.3V 3 2Kx 16 DUAL-PORT STATIC RAM In te g ra te d D e vice T e ch n o lo g y, Inc. FEATURES: • • True Dual-Ported memory cells which allow simulta­ neous access of the same memory location • High-speed access — Commercial: 25/35/55ns max.

Contextual Info: PRELIMINARY IDT709089S/L HIGH-SPEED 64K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Integrated Device Technology, Inc. FEATURES: • • • • • • • True Dual-Ported m em ory cells w hich allow sim ulta­ neous access of the sam e m em ory location

Contextual Info: HIGH-SPEED 8 K x 18 DUAL-PORT STATIC RAM PRELIMINARY IDT7035S/L Features * * True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access - * ♦ Com m ercial: 15120ns max. Low-power operation - ♦ ♦ ♦ IDT7035S

Contextual Info: HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM IDT7007S/L I n t e g r a te d D e v iz e T e c h n o lo g y , l i e . FEATURES: more using the M aster/Slave select when cascading more than one d evice • M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave