A32140DX PQ208 Search Results

A1280XL

Abstract: rq20 A1225XL A1240XL A32100DX A32140DX A32200DX A32300DX A3265DX actel a1240
Contextual Info: Integrator Series FPGAs – 1200XL and 3200DX Familes Features Cadence, Escalade, Exemplar, IST, Mentor Graphics, Synopsys and Viewlogic • JTAG 1149.1 Boundary Scan Testing High Capacity • • • • 2,500 to 40,000 logic gates Up to 4 Kbits configurable dual-port SRAM

A1240XL

Abstract: actel a1240 CQFP 172 PIN A3265DX actel cqfp 84
Contextual Info: BACK Integrator Series FPGAs – 1200XL and 3200DX Familes Features Cadence, Escalade, Exemplar, IST, Mentor Graphics, Synopsys and Viewlogic • JTAG 1149.1 Boundary Scan Testing High Capacity • • • • 2,500 to 40,000 logic gates Up to 4 Kbits configurable dual-port SRAM

actel a1240

Abstract: A1240XL
Contextual Info: Integrator Series FPGAs: 1200XL and 3200DX Families Features Cadence, Escalade, Exemplar, IST, Mentor Graphics, Synopsys, and Viewlogic. • IEEE Standard 1149.1 JTAG Boundary Scan Testing. High Capacity • • • • 2,500 to 40,000 Logic Gates Up to 4 Kbits Configurable Dual-Port SRAM

Actel A1225

Abstract: PL84 A1240XL actel a1240 A32140 PQ100C Cadence TQ176 PG176
Contextual Info: ^ c te l - w Integrator Series FPGAs: 1200XL and 3200DX Famüies Features a 4 L. ¡§ Cadence, Escalade, Exemplar, 1ST, Mentor Graphics, Synopsvs, and Viewlogic. High C a p a c ity • IEEE Standard 1149.1 JTAG Boundary Scan Testing.

132-PIN CERAMIC PIN GRID ARRAY CPGA

Abstract: A3265DX Actel A1240 WD109 A1225XL A1240XL A1280XL A32100DX A32140DX A32200DX
Contextual Info: Integrator Series FPGAs – 1200XL and 3200DX Familes Features Cadence, Escalade, Exemplar, IST, Mentor Graphics, Synopsys and Viewlogic • JTAG 1149.1 Boundary Scan Testing High Capacity • • • • 2,500 to 40,000 logic gates Up to 4 Kbits configurable dual-port SRAM

A42MX24

Abstract: AC297 ACTEL PQ160 CQFP 256 PIN actel A1280XL 42MX ACTEL A1240xl A32140DX PQ208 adb 230 CQ256
Contextual Info: Application Note AC297 Migrating from 1200XL and 3200DX to 42MX FPGAs Overview This application note provides the information needed for seamless migration of a design from the 1200XL and 3200DX families to the 42MX family. The Actel 42MX device architecture is based on the Actel 1200XL and 3200DX families; thus, it shares the

Actel a1280

Abstract: 240 pin rqfp drawing A1280 VKS FPGA CQFP 106 Actel A1225 172 pin leaded A1225XL CQ84 A1240XL A1280XL
Contextual Info: Discontinued – v3.0 v3.0 Integrator Series FPGAs: 1200XL and 3200DX Families F ea t u re s G e n e ra l D es c ri p t i o n H ig h C a p ac it y Actel’s Integrator Series FPGAs are the first programmable logic devices optimized for high-speed system logic

Contextual Info: Integrator Series FPGAs - 1200XL and 3200DX Famüies Features Cadence, Escalade, Exemplar, 1ST, M entor Graphics, Synopsys and Viewlogic High C a p a c ity • JTAG1149.1 Boundary Scan Testing • 2,500 to 40,000 logic gates • Up to 4 Kbits configurable dual-port SRAM

GHL 8

Abstract: FPGA 144 CPGA 172 PLCC ASIC actel a1240 a1280xlf
Contextual Info: Integrator SeriesFPGAs: 1200XL and 3200DX Families Features Cadence, Escalade, E xem plar, 1ST, M e n to r G raphics, Synopsys, and V iew logic. High C a p a c i t y • • 2,500 to 40,000 Logic Gates • Up to 4 K b its C o n fig u ra b le D ual-Port SRAM

Contextual Info: Integrator Series FPGAs - 1200XL and 3200DX Familes Features Cadence, Escalade, Exemplar, 1ST, Mentor Graphics, Synopsys and Viewlogic H ig h C a p a c ity • JTAG 1149.1 Boundary Scan Testing • 2,500 to 40,000 logic gates • Up to 4 Kbits configurable dual-port SRAM

Actel a1280

Abstract: VKS FPGA CQFP 106 wd5080 74 series family A1280 A32200DX-RQ208 Actel A1225 A1225XL A1240XL A1280XL
Contextual Info: v3.0 Integrator Series FPGAs: 1200XL and 3200DX Families Fe a t ur es G en er al D e sc r i p t i on High C apaci t y Actel’s Integrator Series FPGAs are the first programmable logic devices optimized for high-speed system logic integration. Based on Actel’s proprietary antifuse

actel a1240

Contextual Info: Advanced 3.0 Integrator Series FPGAs: 1200XL and 3200DX Families Fe a t ur es • IEEE Standard 1149.1 JTAG Boundary Scan Testing. High C apaci t y • • • • G en er al D e sc r i p t i on 2,500 to 30,000 Logic Gates Up to 3Kbits Configurable Dual-Port SRAM

Pl84

Contextual Info: Component Selector Guide April 1999 1999 Actel Corporation 1 Package Speed Grade SRAM Bits JTAG I/O 3.3 Volt 5 Volt PCI 5.0 Volt Tolerant at 3.3V VQ100 Std, –1, –2, –3 78 8,000 256 512 — — Yes Yes — — Yes PQ208 Std, –1, –2, –3 129 8,000

CQ256

Abstract: CQ208 4PMX 4pm smd
Contextual Info: te /e • / Speed Grade JTAG I/O 3.3 Volt 5 Volt PCI 5.0 Volt Tolerant at 3.3V VQ100 Std, - 1 , - 2 , - 3 129 8,000 256 512 - — Yes Yes — — Yes PQ208 Std, - 1 , - 2 , - 3 129 8,000 256 512 — — Yes Yes — — Yes TQ144 Std, - 1 , - 2 , - 3 129 8,000

Contextual Info: I ntegrator Series FPGAs - 1200XL and 3200DX Fami Ies Cadence, Escalade, Exemplar, 1ST, Mentor Graphics, Synopsysand Vi ewl ogi c • JTAG 1149.1 Boundary Scan Testing Features High C a p a c i t y • • • • 2,5001o 40,0001ogi c gat es Up to 4 Kbits configurable dual-port SRAM

RT54SX72SCQ208

Abstract: A42MX16 RT54SX32S-CQ208 CQ208 CQ256
Contextual Info: v3.0 Component Selector Guide PCI 5.0 Volt Tolerant — 5 Volt I/O — Yes Yes Yes — — Yes 3.3 Volt I/O 3,000 2.5 Volt I/O Gates 36 JTAG I/O User I/O C, I SRAM Bits Screening –F, Std, –P Wide Decodes Speed Grade CS49 Flip-Flops/Dedicated Max Package

baugh-wooley multiplier verilog

Abstract: 1BG25 LPQ100 9572xv BC356 LPQ240 block diagram baugh-wooley multiplier 4 BIT ALU design with vhdl code using structural XC3000A actel a1240
Contextual Info: LeonardoSpectrum Synthesis and Technology v1999.1 Copyright Copyright 1991-1999 Exemplar Logic, Inc., A Mentor Graphics Company All Rights Reserved Trademarks Exemplar Logic and its Logo are trademarks of Exemplar Logic, Inc. LeonardoSpectrum™, LeonardoInsight™, FlowTabs™, HdlInventor™, SmartScripts™,