PL84 Search Results

PL84-WDRG1213

Abstract: PL84
Contextual Info: P-tec Corp. Tel: 800 688-0613 2405 Commerce Circle Tel:(719) 589 3122 Alamosa Co. 81101 Fax:(719) 589 3592 www.p-tec.net sales@p-tec.net PL84 Series Bi-Color 3 Leaded 5mm (T1¾) LED Features Absolute Maximum Ratings at TA = 25°C *Popular 5mm Lens Style with

PL84

Contextual Info: P-tec Corp. Tel: 800 688-0613 2405 Commerce Circle Tel:(719) 589 3122 Alamosa Co. 81101 Fax:(719) 589 3592 www.p-tec.net sales@p-tec.net PL84 Series Bi-Color 3 Leaded 5mm (T1¾) LED Absolute Maximum Ratings at TA = 25°C Features *Popular 5mm Lens Style with

PL84

Contextual Info: page 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PL84 sheet 1 1 1 2 2 2 3 3 3 4 4 4 A B C D E F G date 1956.03.03 1957.03.03 1960.06.06 1956.03.03 1957.03.03 1960.06.06 1957.03.03 1957.08.08 1960.06.06 1957.03.03 1957.08.08 1960.06.06 1960.06.06 1960.06.06

PL84

Abstract: 5mm red super bright led white
Contextual Info: P-tec Corp. Tel: 800 688-0613 2405 Commerce Circle Tel:(719) 589 3122 Alamosa Co. 81101 Fax:(719) 589 3592 www.p-tec.net sales@p-tec.net PL84 Series Bi-Color 3 Leaded 5mm (T1¾) LED Features Absolute Maximum Ratings at TA = 25°C *Popular 5mm Lens Style with

PL84

Contextual Info: PL84 page 1 2 3 4 5 sheet 1 2 3 4 FP date 1969.12 1969.01 1969.01 1969.01 1999.03.19

vq80

Abstract: A40MX02 one time
Contextual Info: Revision 3 40MX and 42MX Automotive FPGA Families Features High Capacity Ease of Integration • Single-Chip Applications ASIC Alternative for Automotive • Up to 100% Resource Utilization and 100% Pin Locking • 3,000 to 54,000 System Gates • Deterministic, User-Controllable Timing

QL3012

Abstract: PF100 PF144 PL84 QL3012-1PF100C QL3012-1PQ144C
Contextual Info: QL3012 - pASIC 3 FPGATM 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density QL3012 - pASIC 3 FPGA DEVICE HIGHLIGHTS Device Highlights High Performance & High Density • 12,000 Usable PLD Gates with 118 I/Os ■ 16-bit counter speeds over 300 MHz, data path speeds over

Actel A1225

Abstract: PL84 A1240XL actel a1240 A32140 PQ100C Cadence TQ176 PG176
Contextual Info: ^ c te l - w Integrator Series FPGAs: 1200XL and 3200DX Famüies Features a 4 L. ¡§ Cadence, Escalade, Exemplar, 1ST, Mentor Graphics, Synopsvs, and Viewlogic. High C a p a c ity • IEEE Standard 1149.1 JTAG Boundary Scan Testing.

ph82

Abstract: ph84 PL83 EM78P350N EM78P350NK EM78P350NM EM78P350NP PH67
Contextual Info: EM78P350N 8-Bit Microprocessor with OTP ROM Product Specification DOC. VERSION 1.0 ELAN MICROELECTRONICS CORP. September 2006 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation.

IDT72V90823

Abstract: RX15
Contextual Info: PRELIMINARY IDT72V90823 3.3 VOLT Time Slot Interchange Digital Switch 2,048 x 2,048 FEATURES: • • • • • • • • • • • • • • 2,048 x 2,048 channel non-blocking switching at 8.192 Mb/s Per-channel variable or constant throughput delay

Contextual Info: Integrator Series FPGAs - 1200XL and 3200DX Famüies Features Cadence, Escalade, Exemplar, 1ST, M entor Graphics, Synopsys and Viewlogic High C a p a c ity • JTAG1149.1 Boundary Scan Testing • 2,500 to 40,000 logic gates • Up to 4 Kbits configurable dual-port SRAM

16X24B

Abstract: CF160 PF100 PF144 PL84 CPGA Package Diagram
Contextual Info: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

PL84

Abstract: ql16x24bl PF100 PF144
Contextual Info: QL16x24BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5V Tolerant I/Os – Support interface to 5 Volt CMOS, NMOS and

QL4090

Abstract: pASIC 1 Family 160CQFP 208-CQFP
Contextual Info: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

Contextual Info: QL3004 pASIC 3 FPGA Data Sheet •••••• 4,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 4,000 Usable PLD Gates with 82 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths

Contextual Info: QL4009 - QuickRAMTM 9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density, and Embedded RAM last updated 5/17/2000 QL4009 - QuickRAM DEVICE HIGHLIGHTS Device Highlights High Performance & High Density • 9,000 Usable PLD Gates with 82 I/Os ■

Contextual Info: QL4009 9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density, and Embedded RAM Last Updated: October 25 1999 QuickRAM HIGHLIGHTS … 9,000 usable PLD gates, 82 I/O pins High Performance and High Density - 9,000 Usable PLD Gates with 82 I/Os - 300 MHz 16-bit Counters, 400 MHz Datapaths, 160+ MHz FIFOs

Contextual Info: QL4009 - QuickRAMTM 9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density, and Embedded RAM last updated 4/5/2000 QL4009 - QuickRAM DEVICE HIGHLIGHTS Device Highlights High Performance & High Density • 9,000 Usable PLD Gates with 82 I/Os ■

Contextual Info: QL3012 - pASIC 3 FPGATM 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density last updated 5/17/2000 QL3012 - pASIC 3 FPGA DEVICE HIGHLIGHTS Device Highlights High Performance & High Density • 12,000 Usable PLD Gates with 118 I/Os

Contextual Info: QL4016 QuickRAM Data Sheet • • • • • • 16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights Advanced I/O Capabilities • Interfaces with both 3.3 V and 5.0 V devices High Performance & High Density

84-PIN

Abstract: PF144 PL84 PQ208 QL2007 QL2007-1PF144C QL2007-1PQ208C 208-Pin PQFP
Contextual Info: QL2007  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. E pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance

Contextual Info: QL3004 4,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Last Updated August 31, 1999 4 pASIC 3 HIGHLIGHTS … 4,000 usable PLD gates, 82 I/O pins High Performance and High Density -4,000 Usable PLD Gates with 82 I/Os -16-bit counter speeds over 300 MHz, data path speeds over 400 MHz

Contextual Info: Prelim inary Data Sheet R e v i s i o n 1.1 IntegratorSeriesFPGAs: 4 0 M X a n d 4 2 MX Families Features • D e te rm in is tic , U ser-C ontrollable T im in g Via D ire ctT im e S oftw are Tools. • M X D iagnostics and Debug S upported b y S ilic o n E xplorer.

H9723

Abstract: h9740 l9718 L9712 L9709 L9727 T9934 l9731 L9706 l9735
Contextual Info: INTEGRATED DEVICE TECHNOLOGY, INC. QUALITY & RELIABILITY MONITORS April 1998 2975 Stender Way, Santa Clara, CA 95054 TEL: 800 345-7015 FAX: (408) 492-8674 QUALITY & RELIABILITY MONITOR REPORT April 1998 TABLE OF CONTENTS Section I: Introduction Section II: