AD9520 Search Results

Contextual Info: Data Sheet 12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO AD9520-4 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4

Contextual Info: Data Sheet 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO AD9520-0 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4

Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator AD9520-5 FUNCTIONAL BLOCK DIAGRAM FEATURES APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710

Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2 GHz VCO AD9520-3 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710

AD9520

Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2 GHz VCO AD9520-3 APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710 Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

AD9520

Abstract: 569f
Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO AD9520-2 APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710

AD9520

Abstract: frequency divider
Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator AD9520-5 FEATURES APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710 Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

AD9520

Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO AD9520-0 APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710

Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO AD9520-2 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710

Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO AD9520-4 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710

AD9520-1

Abstract: intel i9 AD9520
Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.5 GHz VCO AD9520-1 APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710

AD9520-x

Abstract: AD9516 AD9520 AD9522 CR10 AD9520Eval
Contextual Info: Evaluation Board User Guide UG-076 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com AD9520-x Evaluation Board FEATURES GENERAL DESCRIPTION Simple power connection using 6 V wall adapter and

Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator AD9520-5 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM CP REFIN REF2 CLK CLK DIVIDER AND MUXES ZERO DELAY LVPECL/ CMOS DIV/Φ OUT0 OUT1 OUT2 DIV/Φ OUT3 OUT4 OUT5 DIV/Φ OUT6 OUT7 OUT8 DIV/Φ OUT9 OUT10 OUT11 SPI/I2C CONTROL

Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.5 GHz VCO AD9520-1 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710

Contextual Info: Data Sheet 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO AD9520-2 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4

Contextual Info: Data Sheet 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.5 GHz VCO AD9520-1 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4

Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO AD9520-0 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710

TCO-2112

Abstract: AD9516
Contextual Info: 14-Output Clock Generator AD9516-5 FEATURES APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers

max9291

Abstract: AD6643-200 CP-64-4 901MH AN83-5 10-com 1401M 10True
Contextual Info: Dual IF Receiver AD6643 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD AD6643 VIN+A VIN–A PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 VCM VIN+B VIN–B PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 DATA MULTIPLEXER AND LVDS DRIVERS DCO± D0±

E19 CORE TRANSFORMER

Abstract: CP-48-1 AD9524
Contextual Info: 80 MHz Bandwidth, Dual IF Receiver AD6673 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD DVDD AGND DGND DRGND AD6673 VIN+A VIN–A PIPELINE 11-BIT ADC JESD-204B INTERFACE NSR VCM VIN+B VIN–B SYSREF± SYNCINB± CLK± RFCLK PIPELINE 11-BIT ADC HIGH

AD9250

Abstract: E19 CORE TRANSFORMER AD9524 upstream docsis cmts JESD204B
Contextual Info: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter AD9250 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM DVDD AGND DGND DRGND AD9250 VIN+A VIN–A PIPELINE 14-BIT ADC VCM VIN+B VIN–B PIPELINE 14-BIT ADC JESD-204B INTERFACE SERDOUT0± CML, TX

max8895

Abstract: AD9613BCPZ-250
Contextual Info: FEATURES SNR = 69.6 dBFS at 185 MHz fIN and 250 MSPS SFDR = 86 dBc at 185 MHz fIN and 250 MSPS −149.9 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and 250 MSPS Total power consumption: 770 mW at 250 MSPS 1.8 V supply voltages LVDS ANSI-644 levels outputs

AD9467

Abstract: B0205F5050A00 AD520* differential amplifier
Contextual Info: 16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter AD9467 Data Sheet 75.5 dBFS SNR to 210 MHz at 250 MSPS 90 dBFS SFDR to 300 MHz at 250 MSPS SFDR at 170 MHz at 250 MSPS 92 dBFS at −1 dBFS 100 dBFS at −2 dBFS 60 fs rms jitter Excellent linearity at 250 MSPS

circuit diagram of analog clock using logic gates

Contextual Info: FEATURES SNR = 70.6 dBFS at 185 MHz AIN and 250 MSPS SFDR = 85 dBc at 185 MHz AIN and 250 MSPS −151.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and 250 MSPS Total power consumption: 785 mW at 250 MSPS 1.8 V supply voltages LVDS ANSI-644 levels outputs