AD9523BCPZ Search Results

Contextual Info: Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs AD9523 FEATURES APPLICATIONS LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM Output frequency: <1 MHz to 1 GHz Start-up frequency accuracy: <±100 ppm determined by VCXO reference accuracy Zero delay operation Input-to-output edge timing: <150 ps 14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS

ad9523

Abstract: cvhd-950 LVDS I2C EEPROM JESD51-2 differential phase detector divide-by-11
Contextual Info: Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs AD9523 FEATURES APPLICATIONS LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

Contextual Info: Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs AD9523 FUNCTIONAL BLOCK DIAGRAM FEATURES APPLICATIONS LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

Contextual Info: Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs AD9523 FEATURES APPLICATIONS LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs