AL20R Search Results

Contextual Info: Lattice G AL20RA10 High-Speed Asynchronous E2CMOS PLD Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E’CM O S* TECHNOLOGY — 12 ns Maximum Propagation Delay — Fmax =71.4 MHz — 12 ns Maximum from Clock Input to Data Output

L20r

Contextual Info: TIBPAL20L8-20M, AL20R4 20M, AL20RB-20M, AL20R8 20M TIBPAL20L8-15C, AL20R4-15C, AL20R615C, AL20R8 15C HIGH PERFORMANCE IMPACT1*PAL CIRCUITS D 2 9 2 0 , JUNE 1 9 8 6 -R E V IS E D DECEMBER 1 9 8 7 • High Performance: fmax feedback

Q2025H

Abstract: GAL20V8 PAL20R8 PALCE20V8 PAL20L2 programming specification PALCE20v8h gal20v8 amd
Contextual Info: COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25. Q-20/25 MIL: H-15/20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic H Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Pin, function and fuse-map compatible with all GAL 20V8/AS

GAL20RA10-30LP

Abstract: gal20ra10-15lp
Contextual Info: Lattice AL20RA10 High-Speed Asynchronous E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE PC M O S* TECHNOLOGY — 12 ns Maximum Propagation Delay — Fmax =71.4 MHz — 12 ns Maximum from Clock Input to Data Output

C1B92

Abstract: GAL20ra10 gal20ra10-15lp
Contextual Info: LATTICE SEMICONDUCTOR 47E ¡Lattice D • 53flbclL»cl D D 0 2 0 M Û fi ■ LAT G A L20R A 10 High-Speed Asynchronous E2CMOS PLD Generic Array Logic F U N C T IO N A L B L O C K D IA G R A M FEATURES T -*/6-19-01 • HIGH PERFORMANCE E2CMOS* TECHNOLOGY

gal programming specification

Abstract: gal programming algorithm GAL Gate Array Logic AL20R opal GAL20ra10
Contextual Info: AL20RA10 0 3 National m M Semiconductor AL20RA10-15, -20, -25 Generic Array Logic General Description Features T he NSC E2C M O S GAL device com bin e s a high per­ fo rm a nce C M OS process w ith e le ctrica lly erasable floating gate technology. Th is program m able m em ory tech n olo gy

HAL16R8

Abstract: AL10H AL20R HAL16R8A
Contextual Info: HAL/ZHAL D evices ProPAL, H ALand Z H A L devices are programmable logic devices that are programmed, marked and functionally tested by M ono­ lithic Memories. Our functional testing offers the user boardready product at quality levels as stringent as 50 Parts Per Million

GAL20ra10

Contextual Info: Lattice' Semiconductor Corporation FEATURES • HIGH PERFORM ANCE E*CMOS* TECHNOLOGY — 20 ns Maximum Propagation Delay — Fmax =41.7 MHz — 20 ns Maximum from Clock Input to Data Output — TTL Compatible 8 mA Outputs — UltraMOS* Advanced CMOS Technology

Contextual Info: AL20R8 Family 20L8, 20R 8 20 R 6, 2 0 R 4 Featu re s /B e n e fits Perform ance • Standard 24-pin architectures Several speed/pow er versions are available. • T T L and C M O S versions • High speed, as fast as 15 ns tPD for AL20R8B Series • Low power, as low as zero standby for PALC20R8Z Series

Contextual Info: Lattice Semiconductor AL20RA10 High Performance E2CMOS Generic Array Logic Corporation™ FEATURES FUNCTIONAL BLOCK DIAGRAM ypL □ - • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 15 ns Maximum Propagation Delay — Fmax = 50 MHz — 15 ns Maximum from Clock Input to Data Output

Contextual Info: Lattice AL20RA10 High-Speed Asynchronous E2CMOS PLD Generic Array Logic ; Semiconductor I Corporation FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 83.3 MHz — 9 ns Maximum from Clock Input to Data Output

Contextual Info: FINAL COM’L: -5/7/B/B-2/A, 10/2 a Advanced Micro Devices AL20R8 Family 24-Pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • 5-ns propagation delay ■ Power-up reset for initialization ■ Popular 24-pin architectures: 20L8, 20R8, 20R6, 20R4

gal20

Abstract: GAL20ra10
Contextual Info: AL20RA10 Lattice High-Speed Asynchronous E2CMOS PLD Generic Array Logic Semiconductor Corporation FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 83.3 MHz — 9 ns Maximum from Clock Input to Data Output

triac tag 8518

Abstract: 70146 DS3654 X2864AD 7 segment display RL S5220 TC9160 la 4440 amplifier circuit diagram 300 watt philips ecg master replacement guide vtl 3829 A-C4 TCA965 equivalent
Contextual Info: 1985 0 / 0 / CONTENTS VOLUME I Introduction to IC MASTER 3 Advertisers’ Index 8 Master Selection Guide Function Index I0 Part Number Index 40 Part Number Guide 300 Logo Guide 346 Application Note Directory 349 Military Parts Directory 50I Testing 506 Cross Reference

PALC16L8Q

Abstract: PAL20RP4B 8Z35 L16R ic 5209 L16L8A 6R6D PALC20L8 pal8l14 PAL10L8
Contextual Info: PAL/PLD D evice Menu STANDBY SPEED tpo in ns (m&) DATA S H E E T P A G E NO. IN PUTS OUTPUTS PRODUCT T E R M S /O U T P U T PAL8L14A PAL6L16A 8 6 14 16 1 1 25 25 90 90 5-141 5-141 PAL10H8 PAL12H6 PAL14H4 PAL16H2 PAL10L8 PAL12L6 PAL14L4 PAL16L2 PAL16C1 10

Contextual Info: MIL: -10/12/15/B/A COM’L: -5/7/B/B-2/A, 10/2 Advanced Micro Devices AL20R8 Family 24-Pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • As fast as 5 ns maximum propagation delay ■ Power-up reset for initialization ■ Popular 24-pin architectures: 20L8.20R8,

TIBPAL20R4-10C

Contextual Info: TIBPAL20L8-12M, AL20R4 12M, AL20R6-12M. AL20R8-12M TIBPAL20L8-10C, AL20R4-10C, AL20R6 10C, AL20R8-10C HIGH-PERFORMANCE IMPACT X m PAL CIRCUITS D 3 3 3 6 , OCTOBER 1 9 8 9 High-Performance Operation: fmax w/o feedback AL20R-10C Series . . . 71.4 MHz

Contextual Info: Asynchronous AL20RA10 Ordering Information Features/ Benefits • Programmable clock for asynchronous operation AL20RA10-20 C NS STD • Programmable asynchronous set and reset • Programmable polarity PROGRAMMABLE ARRAY LOGIC T L PROCESSING STD = Standard

ot31

Abstract: PAL20L8A PAL20L8 programming specifications PAL20R4A PAL20R6A-2 PAL20R8A PAL VIHH programming pulse PAL20 PAL20L8 PAL20R4
Contextual Info: P A L2 0 L8 A , P A L2 0 R 4 A , P A L2 0 R 6 A , P A L2 0 R 8 A S T A N D A R D H IG H S P E E D PAL C IR C U IT S D 2 7 0 6 , DECEMBER 1 9 8 2 -R E V IS E D DECEMBER 1987 S tandard High Speed 2 5 ns PAL Fam ily • C hoice o f In p u t/O u tp u t C onfiguration

gal20ra10-15lp

Abstract: GAL20RA10-20LP 24-Pin GAL Plastic DIP GAL20ra10
Contextual Info: Lattice G A L20R A 10 High-Speed Asynchronous E2CMOS PLD Generic Array Logic F U N C T IO N A L B L O C K D IA G R A M FEATURES • HIGH PERFORMANCE E*CMOS* TECHNOLOGY — 12 ns Maximum Propagation Delay — Fmax = 71.4 MHz — 12 ns Maximum from Clock Input to Data Output

pal20l8b

Abstract: pal 20 medium
Contextual Info: Semiconductor Programmable Array Logic PAL 24-Pin Medium PAL Family General Description The 24-pin Medium PAL family contains four of the most popular PAL architectures with speeds as fast as 10 ns maximum propagation delay. National Semiconductor's ad­