AM25LS Search Results

LS244

Abstract: applications of 74LS244 74LS244 LOGIC DESCRIPTION 74LS244 LS241 74LS244 20 pin of 74LS244 74ls244 as buffer
Contextual Info: Am25LS241 • Arr»54LS/74LS241 Am25LS244• Am54LS/74LS244 O c ta l T h re e -S ta te B uffers DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • • • • • • • • The 'LS241 and 'LS244 are octal buffers fabricated using advanced low-pow er Schottky technology. The 20-pin pack­

Contextual Info: 60SHSZUUV Am 25LS09 Quad Two-Input, High-Speed Register DISTINCTIVE CHARACTERISTICS • • • 4-bit register accepts data from one-of-two 4-bit input fields Edge triggered clock action Second sourced by T.l. as 54LS/74LS399 Am25LS D.C. parameters including:

alu 74ls181

Abstract: 74LS181 Alu 181
Contextual Info: Am25LS181 • Am54LS/74LS181 Four-Bit Arithmetic Logic Unit/Function Generator L O G IC D I A G R A M D I S T IN C T I V E C H A R A C T E R IS T IC S • • • • P erform s 16 a rith m e tic o pe ra tio ns in c lu d in g add, su b tra ct, d o u b le and com pare

register file

Abstract: LS670 74LS670 74LSI70
Contextual Info: Am25LS670 • Am54LS/74LS670 4-By-4 Register File with 3-State or Open Collector Outputs Am25LS670 • Am54LS/74LS670 data is combined with the Am25LS170. See Am25LS170 data sheet for full information. F U N C T IO N A L DESCRIPTION T h e A m 2 5 L S 1 7 0 and 6 7 0 are 1 6 -b it lo w -p o w e r S c h o tt k y

Contextual Info: Am25LS194A • Am54LS/74LS194A Am25LS195A • Am54LS/74LS195A Four-Bit High-Speed Shift Registers D IS TIN C TIV E C H AR A C TE R IS TIC S • • • • • LOGIC D IA G R A M S S hift righ t or parallel load w ith JK inputs on A m 25LS 195A S hift le ft, right, parallel load or do nothing on A m 25LS 194A

74LS399

Contextual Info: Arrt25LS09 Am25LS09 Quad Two-Input, High-Speed Register DISTINCTIVE CHARACTERISTICS • • • 4-bit register accepts data from one-of-two 4-bit input fields Edge triggered clock action Second sourced by T.l. as 54LS/74LS399 Am25LS D.C. parameters including:

QE Logica 21

Abstract: 74ls164 74LS164 PIN DIAGRAM ad 440J AM25LS164DM 74ls gate symbols SN74LS164 74LS AM25LS164DC LS164
Contextual Info: Am25LS164 • Am54LS/74LS164 8-Bit Serial-ln, Parallel-Out Shift Register D IS T IN C T IV E C H A R A C T E R IS T IC S F U N C T I O N A L D E S C R IP T I O N • • T h e A m 2 5 L S 1 6 4 and A m 5 4 L S / 7 4 L S 1 64 are e ight-b it, serial in/parallel o u t sh ift registers bu ilt using advanced Low -Po w er

74LS190 up down decade counter

Abstract: 74LS190 PIN diagram 74LS190 pins 74LS190 ad 440J 74LS190 APPLICATIONS function 74ls190 74LS190 application
Contextual Info: Am25LS190 • Am54LS/74LS190 Am25LS191 • Am54LS/74LS191 Synchronous Counters With Up/Down Mode Control LO G IC D IA G R A M S D IS T IN C T IV E C H A R A C T E R IS T IC S • • • Single u p /d o w n c o u n tlin e Parallel load in p u ts and parallel c o u n t o u tp u ts

LS168A

Abstract: LS-168a LS168 sn74ls169an LS169A 74LS168 application note 25ls 74ls 74LS169A
Contextual Info: Am25LS168A • Am25LS169A Am54LS/74LS168A • Am54LS/74LS169A Synchronous Four-Bit Programmable Up-Down Counter F U N C T IO N A L D E S C R IP T IO N D IS T IN C T IV E C H A R A C T E R IS T IC S • • • • • A ll o p e ra tio n s are syn ch ro n o u s

LS251

Abstract: 74LS151 multiplexers 74 LS 150 LS 74LS151 pin diagram 41 multiplexer 74ls151 74 LS 151 Logic DIAGRAM eight input multiplexer 54LS251 74LS1 74LS251
Contextual Info: Am25LS151 • Am54LS/74LS151 Am25LS251 • Am54LS/74LS251 Eight-Input Multiplexers L O G IC D IA G R A M D IS T IN C T IV E C H A R A C T E R IS T IC S • • • • S w itches o n e -o f-e ig h t in p u ts to tw o co m p le m e n ta ry o u tp u ts S ta n d ard , 'L S 15 1 and three-state, 'L S 25 1 o u tp u t versions

AM25LS2519

Contextual Info: Am25LS2519 \ Am 25LS2519 Quad Register with Two Independently Controlled Three-State Outputs DISTINCTIVE CHARACTERISTICS • • • • Buffered com m on asynchronous clear S e p arate buffered com m on output enable for each set of outputs Tw o sets o f fully buffered three-state outputs

Contextual Info: Am25LS2538 Am25LS2538 One-of-Eight Decoder with Three-State Outputs and Polarity Control DISTINCTIVE CHARACTERISTICS • • • Three-state decoder outputs Buffered com m on output polarity control Inverting and non-inverting enable inputs A. C. param eters specified over operating tem perature

bj 950 131- 6

Abstract: 74LS385 "serial adder" Am25LS14 serial adder AM25LS15PC bj 945 25ls22
Contextual Info: Am25LS15 Am25LS15 Quad Serial Adder/Subtractor DISTINCTIVE CHARACTERISTICS • • M a g n itu d e o n ly a d d itio n /s u b tra c tio n S e c o n d s o u rc e d b y T .l. a s A m 5 4 L S /7 4 L S 3 8 5 F o u r in d e p e n d e n t a d d e r/s u b tra c to rs

LS2520

Abstract: Am26l-S2520
Contextual Info: Am25LS2520 Am25LS2520 Octal D-Type Flip-Flop with Clear, Clock Enable and Three-State Control DISTINCTIVE CHARACTERISTICS • • 8-bit, high-speed parallel register w ith positive edgetriggered, D-type flip-flops Am25LS Family offers improved sink current, source

Contextual Info: Am25LS15 Am25LS15 Quad Serial Adder/Subtractor DISTINCTIVE CHARACTERISTICS • • Magnitude only addition/subtraction Second sourced by T.l. as Am54LS/74LS385 Four independent adder/subtractors Use with two's complement arithmetic GENERAL DESCRIPTION The Am25LS15 is a serial two's complement adder/

Contextual Info: Am25LS138 • Am54LS/74LS138 3-Line To 8-Line Decoder/Demultiplexer D IS T IN C T IV E C H A R A C T E R IS T IC S L O G IC D IA G R A M • Inverting and non-inverting enable inputs • A m 2 5 L S devices offer the following improvements over Am 54/74LS

Contextual Info: Am25LS14A Am25LSl4A 8-Bit Serial/Parallel Two's Complement Multiplier DISTINCTIVE CHARACTERISTICS • • • • Two's complement multiplication without correction Magnitude only multiplication Cascadable for any number of bits 8-bit parallel multiplicand data input

74LS534

Abstract: SN74LS534N 74LS53 74LS SN74LS534 4LS374 SN74LS374AN
Contextual Info: Am25LS374A • Am54LS/74LS374A Am25LS534 • Am54LS/74LS534 8-Bit Registers with Three-State Outputs DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • 8-bit, high-speed parallel registers • Positive, edge-triggered, D-type flip-flops • Buffered common clock and buffered common three-state

Contextual Info: Am25LS241 • Am54LS/74LS241 Am25LS244• Am54LS/74LS244 Octal Three-State Buffers DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • T h re e -s ta te o u tp u ts d riv e bus lines directly • H ysteresis at inputs im p ro v e noise m argin • PNP inputs red uce D.C. lo ad ing on bus lines

74LS281

Abstract: AM25LS281
Contextual Info: Am25LS281 • Am54LS/74LS281 4-Bit Parallel Binary Accumulator F U N C T IO N A L D E S C R IP T IO N D I S T I N C T IV E C H A R A C T E R I S T I C S • • • • • • Four-bit binary accum ulator Fifteen-function A L U 8 arithm etic functions 7 logic functions

25LS09

Contextual Info: Am25LS09 Quad Two-Input, High-Speed Register DISTINCTIVE CHARACTERISTICS 4-bit register accepts data from one-of-two 4-bit input fields Edge triggered clock action Second sourced by T.l. as 54LS/74LS399 Am25LS D.C. parameters including: - Vol “ 0.45V at Iol “ 8mA

AM25LS2538

Contextual Info: Am25LS2538 Am25LS2538 One-of-Eight Decoder with Three-State Outputs and Polarity Control DISTINCTIVE CHARACTERISTICS • • • Three-state decoder outputs Buffered common output polarity control Inverting and non-inverting enable inputs A. C. parameters specified over operating temperature

74LS164

Abstract: 25LS164 QE Logica 21
Contextual Info: Am25LS164 • Am54LS/74LS164 8-Bit Serial-ln, Parallel-Out Shift Register D IS T IN C T IV E C H AR AC TER ISTIC S F U N C T IO N A L DESCRIPTION • • Gated serial inputs Asynchronous clear • A m 25LS devices o ffe r the follow ing improvements over A m 54/74 LS

THR9

Contextual Info: Am 25LS23 8-Bit Shift/Storage Register with Synchronous Clear DISTINCTIVE CHARACTERISTICS • • • Cascadable shifting Second sourced by T.l. as 54LS/74LS323 Synchronous clear Three-state outputs Common input/output pins GENERAL DESCRIPTION The Am25LS23 is an 8-bit universal shift/storage register