AM8167 Search Results

2B0365

Abstract: 74ls244 latch ic Z8127 z80 multibus Am286
Contextual Info: Am8163/Am8167 A m 816 3 /A m 816 7 Dynamic Memory Timing, Refresh and EDC Controllers DISTINCTIVE CHARACTERISTICS • Complete CPU to dynamic RAM control interface • R A S /M S E L/C A S Sequencer to eliminate delay lines • Complete EDC/data path controls for W ord/Byte read

Contextual Info: Am8163/Am8167 Am8163/Am8167 Dynamic Memory Timing, Refresh and EDC Controllers DISTINCTIVE CHARACTERISTICS • • • • Complete CPU to dynamic RAM control Interface RAS/MSEL/óÀS Sequencer to eliminate delay lines Complete EDC/data path controls for Word/Byte read

str f 6167

Abstract: amz8127 str 6167 supi 3 ls z80b Am8001 AM8163 IC HS 8167 z80 multibus 74LS240
Contextual Info: Am8163/Am8167 A m 8 1 6 3 /A m 8 1 6 7 Dynamic Memory Timing, Refresh and EDC Controllers DISTINCTIVE CHARACTERISTICS EDC error flag latches for error logging under software control Two timing configurations support a broad range of processors Z80, Z8000, 8086, 8088, MC68000

am8160

Abstract: str f 6167 Amz8127 74LS240 MC68000 Z8000 Z80A Z80B 50lh 71p3ns
Contextual Info: Am8163/Am8167 Am 8163/Am 8167 Dynamic Memory Timing, Refresh and EDC Controllers DISTINCTIVE CHARACTERISTICS EDC error flag latches for error logging under software control Two timing configurations support a broad range of processors Z80, Z8000, 8086, 8088, MC68000