ASX4 Search Results

Contextual Info: ASX415 250 ~ 4000 MHz MMIC Amplifier 4 Features Description  14 dB Gain at 2000 MHz  27 dBm P1dB at 2000 MHz  42 dBm OIP3 at 2000 MHz  ACLR @ WCDMA 4FA: -51 dBc @ Pout = +13 dBm, +/- 5 MHz offset  MTTF > 100 Years  Single Supply The ASX415, a power amplifier MMIC, has a high

Contextual Info: ASX420 250 ~ 3500 MHz MMIC Amplifier Description Features  31.5 dB Gain at 900 MHz  29.5 dBm P1dB at 900 MHz  47 dBm Output IP3 at 900 MHz  6.8 dB NF at 900 MHz  MTTF > 100 Years  Two Power Supplies The ASX420, a power amplifier MMIC, has a high

zener diode c5

Abstract: Zener C422 zener diode c6 C2 6 zener diode 5-6V Zener Diode Zener Diode C3 5
Contextual Info: ASX401 100 ~ 3000 MHz MMIC Amplifier Features Description  19.5 dB Gain at 900 MHz  29.5 dBm P1dB at 900 MHz  47 dBm Output IP3 at 900 MHz  MTTF > 100 Years  Single Supply The ASX401, a power amplifier MMIC, has a high linearity, high gain, and high efficiency over a wide

diode C339

Contextual Info: ASX423 100 ~ 4500 MHz MMIC Amplifier Description Features  32.5 dB Gain at 900 MHz The ASX423, a power amplifier MMIC, has a high linearity, high gain, and high efficiency over a wide range of frequency, being suitable for use in both receiver and transmitter of telecommunication

Contextual Info: ASX403 400 ~ 3000 MHz MMIC Amplifier Features Description  11 dB Gain at 2000 MHz  29.5 dBm P1dB at 2000 MHz  38.5 dBm OIP3 at 2000 MHz  4.5 dB NF at 2000 MHz  MTTF > 100 Years The ASX403, a power amplifier MMIC, has a high linearity, high gain, and high efficiency over a wide

silicon transistor manual

Abstract: MAX7000S EPF10K10LC84-3 MAX7000 8B10B FLEX10K MAX7000B processor atom gx 6101 d max3000A
Contextual Info: Quartus II Settings File Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com MNL-Q21005-7.0 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

Contextual Info: Stratix V Device Overview 2014.04.08 SV51001 Subscribe Send Feedback Many of the Stratix V devices and features are enabled in the Quartus® II software version 13.0. The remaining devices and features will be enabled in future versions of the Quartus II software.

ASW212

Contextual Info: Gain Block Amplifiers If not specified, the data @ 2 GHz Vd Id (V) (mA) S21 (dB) @ MHz OIP3 OP1dB NF S11 S22 (dBm) (dBm) (dB) (dB) (dB) Part Number ASG330 ASW114 Matching Circuit Frequency Package 900 2000 2400 2700 3500 5800 5.0 75 19.0 10.0 - - - - 43

pcie gen3

Abstract: 28gbps
Contextual Info: Stratix V Device Handbook Volume 1: Overview and Datasheet Stratix V Device Handbook Volume 1: Overview and Datasheet 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V3-1.2 11.0 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.

RF40-F1517

Abstract: SV53001-2 HF35-F1152 5SGX
Contextual Info: Stratix V Device Handbook Volume 1: Overview and Datasheet 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V3-1.7 11.1 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos

HF35-F1152

Abstract: KF40-F1517 5sgxa3 eye-q 400 NF40-F1517 interlaken gf35 NF45 KF35-F1152
Contextual Info: Stratix V Device Family Overview January 2011 SV51001-1.6 SV51001-1.6 This document provides an overview of the Stratix V devices and their features. Many of these devices and features are enabled in the Quartus ® II software version 10.1. The remaining devices and features will be enabled in future versions of the

SV53001-2

Abstract: KF35-F1152 QSFP 40G transceiver RF40-F1517 KF40-F1517 10G SFP HF35-F1152 H40-H1517 5SGXB9
Contextual Info: Stratix V Device Handbook Volume 1: Overview and Datasheet 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V3-1.8 11.1 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos

lpddr2 datasheet

Abstract: lpddr2 QSFP optical active cable D-type Connector 25 Pin UniPHY lpddr2 CCPD 33 CB 100MHz lpddr2 spec tsmc 28nm standard io library lpddr2 phy lpddr2 DQ calibration
Contextual Info: Stratix V Device Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 10.0 July 2010 Copyright © 2010Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words

Contextual Info: 1 CONTENTS Chapter 1 SoCKit Development Kit. . . 4 1.1 Package Contents. 4

Contextual Info: Stratix V Device Overview 2013.05.06 SV51001 Subscribe Feedback Many of the Stratix V devices and features are enabled in the Quartus® II software version 13.0. The remaining devices and features will be enabled in future versions of the Quartus II software.

OPGW

Abstract: optical fiber NZ-DSF opgw 24 18698
Contextual Info: Samsung Electronics Fiberoptics products OPtical Ground Wire Steel Tube Design SAMSUNG OPGW SC-OP200 provides ground wire protection for overhead power lines as well as fiber optic cable for optical communication systems with high performance characteristics. With an innovative engineering design and

ASW204

Contextual Info: Application Note Maximum Input Power Analysis of ASB’s MMIC Amplifiers Maximum Input Power Analysis of MMIC Amplifiers 1. Introduction In many applications, amplifiers may be subjected to an unexpected abnormal operation by a various RF environment so that the amplifier can’t work properly in a system. We made a test to provide a

Contextual Info: Stratix V Device Handbook Volume 1: Overview and Datasheet 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V3-1.6 11.1 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos

lpddr2 datasheet

Abstract: lpddr2 lpddr2 phy lpddr2 spec verilog code 8 bit LFSR in scrambler sgmii sfp cyclone SV51005-1 jesd79-3d lpddr2 DQ calibration QSFP CONNECTOR
Contextual Info: Stratix V Device Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 10.1 January 2011 Copyright © 2011Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words

ASX4

Contextual Info: REVISIONS SYM ZONE AMPHENOL PART NUMBER: U E 2 7 — A S X 4 — X X X ECN, ERN NO. c PROPOSAL APPRD. DATE A p ril 2 5 .0 0 LC H AN -0 = P B T HOUSING H-HIGH TEMP HOUSING e c p ir ç _ UE27=RECEPTACLE TYPE -A=SERIES A -SHIELDING OPTION

100GBASE-R

Abstract: QSFP 40G transceiver 40GBASE-R CPRI multi rate gearbox pcie gen3 QSFP optical active cable QSFP M20K 5SGX
Contextual Info: Stratix V Device Family Overview SV51001-1.3 This document provides an overview of the Stratix V device features. Many of these features are enabled in the Quartus ® II software version 10.0. The remaining features will be enabled in future versions of the Quartus II software.

RF40-F1517

Abstract: KF40-F1517
Contextual Info: Stratix V Device Handbook Volume 1: Overview and Datasheet Stratix V Device Handbook Volume 1: Overview and Datasheet 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V3-1.3 11.0 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.

SV51001-3

Abstract: interlaken 100GBASE-R 5SGXBB HF35-F1152
Contextual Info: Stratix V Device Overview June 2012 SV51001-3.0 SV51001-3.0 This document provides an overview of the Stratix V devices and their features. Many of these devices and features are enabled in the Quartus® II software version 12.0. The remaining devices and features will be enabled in future versions of