ATA24 Search Results

APD, applications, bias supply

Abstract: nortel apd 2-pin ir receiver
Contextual Info: High Performance Optical Component Solutions DATA S H E E T ATA2400-40 2.5Gb/s APD Preamp Receiver Features High sensitivity -34dBm. High dynamic range. High bandwidth. Integral thermistor. Applications Long reach STM16/OC48 receivers. Description The ATA 2400 APD Pre-amp comprises

lr3220

Abstract: lr3000
Contextual Info: LSI LOGIC LR3220 Read-W rite Buffer Preliminary Introduction The LR3220 R e ad -W rite B u ffe r en h a n ce s the pe rfo rm a n ce o f M IPS a rc h ite c tu re -b a s e d sys­ tem s by b u ffe rin g w rite and read o p era tions. Using th e R e ad -W rite Buffer, the system can

parallel data transfer using 8155 chip

Contextual Info: 8155 Security Processor Data Sheet Hifn Confidential DE-0011-05, 10/23/08, Hi/fn , Inc. All rights reserved. 10/08 No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form by any means without the written permission of Hi/fn, Inc. “Hifn”

ma6208

Abstract: LSI05 LS100 MA12 D-11-023 mudata
Contextual Info: LS105 ". I-Cube SATC Controller Features Description • 33 M H z 32-bit PCI bus interface, 8 interrupt lines to support up to 8 LSlOOs. • 32/48 bit Interface with standard asynchronous SRAM to cache up to 64K MAC addresses. • Supports Port based Y L A N with internal port

ATA2400-40C

Abstract: APD, applications, bias supply ir 4021 apd 1550, sensitivity 30 dBm
Contextual Info: Data sheet 2.5 Gb/s APD Preamp Receiver uncooled The 2.5 Gb/s APD Preamp Receiver - uncooled comprises a high speed APD coupled to a non-inverting HBT transimpedance amplifier with a style-ended output. The receiver is housed in an 8 pin butterfly package with

Contextual Info: | ELAN 8X10 V\VI I # I PMC-Sierra, Inc. PM3350 elan 8 x io DATA SHEET PMC-970109 ISSUE 3 8 PORT ETHERNET SWITCH CONTENTS FEATURES. 5 BLOCK

AD27C64

Abstract: I-CUBE D2716-6 100BASE-FX 10BASE2 10BASE5 LS100 AD28C "network interface controller"
Contextual Info: I-Cube* LS10° Quad-Port Ethernet Switch Interface Description Features • Supports both 10 and 100 Mb Ethernet, selectable on a per-port basis • Cut-through or Store-and-Forward switching, selectable on a per-port basis • Supports both Half Duplex and Full Duplex,

ATA07

Abstract: MAX708 pwr ing sd
Contextual Info: EV-48006 Evaluation Board for the GT-48006 Preliminary Revision 1.1 3/9/98 http://www.galileoT.com info@galileoT.com Tel 408 367-1400 Fax (408)367-1401 EV-48006 Evaluation Board for the GT-48006 1. Introduction The EV-48006 Evaluation Board for the GT-48006 implements a 2-port 10/100 Ethernet bridge in a small formfactor.

Contextual Info: 8155 Network Security Processor Device Specification Intelligent Secure Networking Hifn Confidential . DE-0011-02, 5/4/06, Hi/fn , Inc. All rights reserved. 05/06 No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into

AM 35-IMS

Contextual Info: / T T SGS-THOMSON * 7/ 5 ' Œ « s * S IM S G 2 0 0 XGA DISPLAY CONTROLLER IM S G 200 /) $ a5 A ddress bus V n / s - 32 rV .32. V7V S ystem bus interface C oprocessor CD 0 00^ OE C R T and V R AM controller (0 .c o V R A M ad dress bus o 32 A/N font and sprite

Contextual Info: Full D uplex LSI LOGIC 80C300 Full Duplex CMOS Ethernet 10/100 Mega Bit/Sec Data Link Controller 98012 This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic. Note: Check for latest Data Sheet revision before starting any designs.

ECU 206 7.4.5

Abstract: TYN 208 equivalent JRC 2100 15j01 sem 2106 diagram A44D tyn 208 ltw 12 pin circular connector
Contextual Info: ADSP- 2106x SHARCF DSP Microcomputer Family AD6F-21062/ADSF-21062L ANALOG DEVICES SUMMARY High Performance Signal Processor for Communica­ tions, Graphics and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch and Nonintrusive I/O

IS07816-3

Abstract: LPC 248 microcontroller ST20-TP2 st20c2 DVB-C tuner 27mhz remote control transmitter circuit express card DVB LS 5208 pinout ST20 Embedded Toolset ST20 TOOLSET
Contextual Info: w# SGS -THOMSON ^7# MD g[M I[L[I(mi[M)R!]D(gS CTon TDO ST20-TP2 PROGRAMMABLE TRANSPORT 1C FOR DVB APPLICATIONS FEATURES • Enhanced 32-bit VL-RISC CPU 0 to 40 MHz processor clock fast integer/bit operations very high code density ■ 8 Kbytes on-chip SRAM

Contextual Info: 1 Microarchitecture The DECchip 21066 microprocessor implements Digital’s Alpha AXP architecture. The following sections provide an overview of the chip’s architecture and major functional units. Figure 1 is a block diagram of the DECchip 21066 microprocessor.

IT8512

Abstract: GF-GO7600-N-B1 jmb363 CLEVO ITE IT8512 CIR lm3580 z3730 MOSFET IRF 708 Z1507 8 pin ic sdc 3733
Contextual Info: Preface LCD Computer LV22C/LV22N/LV19C/LV19N Series Service Manual Preface I Preface Notice The company reserves the right to revise this publication or to change its contents without notice. Information contained herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent vendor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are

Contextual Info: 8170 Security Processor Data Sheet Hifn Confidential DE-0014-02, 10/23/08, Hi/fn , Inc. All rights reserved. 10/08 No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form by any means without the written permission of Hi/fn, Inc. “Hifn”

D11009

Abstract: 100BASE-FX 10BASE2 10BASE5 LS10 LS100 MCJ1 bidirectional switch "network interface controller"
Contextual Info: i I-Cube LS10° Q uad-Port Ethernet Switch Interface Description Features • Supports both 10 and 100 Mb Ethernet, selectable on a per-port basis • Cut-through or Store-and-Forward switching, selectable on a per-port basis • Supports both Half Duplex and Full Duplex,

GPI05

Abstract: ma6208 mudata lS105 GPI07 TDA 1106
Contextual Info: LS105 ". I-C ube SATC Controller Features Description • 33 M Hz 32-bit PCI bus interface, 8 interrupt lines to support up to 8 LSlOOs. • 32/48 bit Interface with standard asynchronous SRAM to cache up to 64K MAC addresses. • Supports Port based YLAN with internal port

scart to vga

Abstract: schematic diagram of TV memory writer MC 7805 CK samsung crt monitor rgb cable schematic diagram scart to vga IGS003 bdac for cpu IGS TECHNOLOGIES m1d 95 free vga to rca schematic
Contextual Info: CyberPro2010 Data Sheet Revision 2.01 &\EHU3URŒ CyberPro2010 Key Features Multimedia Graphics • 64-bit GUI Graphics • 200 MHz RAMDAC • Shadow register compatibility for popular video Accelerator and games Enhanced Digital TV TV Encoder • 6 on-chip DACS provide simultaneous S-video,