AUTO10 Search Results

EDD2516AETA-5B-E

Abstract: DDR333 DDR400 EDD2516AETA EDD2516AETA-5C-E EDD2516AETA-6B-E EDD2516AETA-7A-E
Contextual Info: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2516AETA 16M words x 16 bits Specifications Features • Density: 256M bits • Organization  4M words × 16 bits × 4 banks • Package: 66-pin plastic TSOP (II)  Lead-free (RoHS compliant) • Power supply:

Contextual Info: ISSI IS43R16800A 8Meg x 16 128-MBIT DDR SDRAM PRELIMINARY INFORMATION JULY 2005 FEATURES DEVICE OVERVIEW • • • • ISSI’s 128-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 134,217,728-bit memory

DDR333

Abstract: IS43R16800A-6
Contextual Info: ISSI IS43R16800A-6 8Meg x 16 128-MBIT DDR SDRAM PRELIMINARY INFORMATION APRIL 2006 FEATURES DEVICE OVERVIEW • • • • ISSI’s 128-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 134,217,728-bit memory

DDR333

Abstract: DDR400 EDD5108AFTA EDD5108AFTA-5B-E EDD5108AFTA-5C-E EDD5108AFTA-6B-E EDD5108AFTA-7A-E EDD5116AFTA
Contextual Info: DATA SHEET 512M bits DDR SDRAM EDD5108AFTA 64M words x 8 bits EDD5116AFTA (32M words × 16 bits) Specifications Features • Density: 512M bits • Organization ⎯ 16M words × 8 bits × 4 banks (EDD5108AFTA) ⎯ 8M words × 16 bits × 4 banks (EDD5116AFTA)

EDD2508AETA-7A-E

Abstract: EDD2516AETA DDR333 DDR400 EDD2508AETA EDD2508AETA-5B-E EDD2508AETA-5C-E EDD2508AETA-6B-E
Contextual Info: DATA SHEET 256M bits DDR SDRAM EDD2508AETA 32M words x 8 bits EDD2516AETA (16M words × 16 bits) Specifications Features • Density: 256M bits • Organization  8M words × 8 bits × 4 banks (EDD2508AETA)  4M words × 16 bits × 4 banks (EDD2516AETA)

Contextual Info: PRELIMINARY DATA SHEET 512M bits DDR SDRAM WTR Wide Temperature Range EDD5108ADTA-TI (64M words x 8 bits) EDD5116ADTA-TI (32M words × 16 bits) Pin Configurations The the EDD5108AD and the EDD5116AD are 512M bits Double Data Rate (DDR) SDRAM. Read and write

resistor mr6

Abstract: SD78K0 IE-78000-R NEC MR31 resistor MR25 resistor mr4 EV-9200GF-100 PD780208 ISS123 auto-10
Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

BA 75 is

Abstract: DDR333 DDR333B DDR400 DDR400B
Contextual Info: PRELIMINARY DATA SHEET 512M bits DDR SDRAM High Quality Product EDD5116AFTA-H 32M words x 16 bits Specifications Features • Density: 512M bits • Organization ⎯ 8M words × 16 bits × 4 banks • Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS compliant)

74S1057

Abstract: 74S1055 ACT374 IE-78000-R bnc to probe clips pal22v10 EV-9200GC-80 MR15 PD178004 auto-10
Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

DDR400

Contextual Info: DATA SHEET 256M bits DDR SDRAM EDD2516AKTA-5-E 16M words x 16 bits, DDR400 Description Pin Configurations The EDD2516AKTA-5 is a 256M bits DDR SDRAM organized as 4,194,304 words × 16 bits × 4 banks. Read and write operations are performed at the cross

EDD1216AATA

Abstract: EDD1216AATA-6B-E
Contextual Info: DATA SHEET 128M bits DDR SDRAM EDD1216AATA 8M words x 16 bits Description Pin Configurations The EDD1216AATA is a 128M bits Double Data Rate (DDR) SDRAM organized as 2,097,154 words × 16 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture. Data strobe (DQS) both for

DDR400

Abstract: EDD1232AAFA-5C-E
Contextual Info: PRELIMINARY DATA SHEET 128M bits DDR SDRAM EDD1232AAFA-5 4M words x 32 bits, DDR400 Description Features The EDD1232AA is a 128M bits DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data

DDR400

Abstract: EDD1232AABH-5C-E
Contextual Info: PRELIMINARY DATA SHEET 128M bits DDR SDRAM EDD1232AABH-5 4M words x 32 bits, DDR400 Description Features The EDD1232AA is a 128M bits DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data

Contextual Info: PRELIMINARY DATA SHEET 128M bits DDR SDRAM EDD1232ABBH 4M words x 32 bits Specifications Features • Density: 128M bits • Organization ⎯ 1M words × 32 bits × 4 banks • Package: 144-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 2.5V ± 0.125V

Contextual Info: PRELIMINARY DATA SHEET 128M bits DDR SDRAM EDD1232AABH-5 4M words x 32 bits, DDR400 Description Features The EDD1232AA is a 128M bits DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data

5bti

Abstract: DDR333 DDR333B DDR400 DDR400B
Contextual Info: PRELIMINARY DATA SHEET 512M bits DDR SDRAM WTR Wide Temperature Range EDD5116AFTA-TI (32M words x 16 bits) Specifications Features • Density: 512M bits • Organization ⎯ 8M words × 16 bits × 4 banks • Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS compliant)

EDD5104ADTA-E

Abstract: EDD5108ADTA-E EDD5116ADTA-E EDD5116ADTA-6B-E
Contextual Info: PRELIMINARY DATA SHEET 512M bits DDR SDRAM EDD5104ADTA-E 128M words x 4 bits EDD5108ADTA-E (64M words × 8 bits) EDD5116ADTA-E (32M words × 16 bits) Pin Configurations The EDD5104AD, the EDD5108AD and the EDD5116AD are 512M bits Double Data Rate (DDR)

DDR333

Abstract: DDR400 EDD5108AFTA EDD5108AFTA-5B-E EDD5108AFTA-5C-E EDD5108AFTA-6B-E EDD5108AFTA-7A-E EDD5116AFTA EDD5116AFTA-5B-E
Contextual Info: DATA SHEET 512M bits DDR SDRAM EDD5108AFTA 64M words x 8 bits EDD5116AFTA (32M words × 16 bits) Features • Density: 512M bits • Organization  16M words × 8 bits × 4 banks (EDD5108AFTA)  8M words × 16 bits × 4 banks (EDD5116AFTA) • Package: 66-pin plastic TSOP (II)

EDD1216AJTA-5B-E

Abstract: DDR400B EDD1216AJTA EDD1216AJTA-5C-E EDD1216AJTA-6B-E
Contextual Info: DATA SHEET 128M bits DDR SDRAM EDD1216AJTA 8M words x 16 bits Features • Density: 128M bits • Organization  2M words × 16 bits × 4 banks • Package: 66-pin plastic TSOP (II)  Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 2.5V ± 0.2V

FSQ510 Equivalent

Abstract: BTA12 6008 bta16 6008 ZIGBEE interface with AVR ATmega16 Precision triac control thermostat thyristor t 558 f eupec gw 5819 diode transistor a564 A564 transistor BSM25GP120 b2
Contextual Info: SEMICONDUCTORS MCU/MPU/DSP Atmel. . . . . . . . . 167, 168, 169, 170, 171, 172 Blackhawk. . . . . . . . . . . . . . . . . . . . . . . . . 173 Cyan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Cypress. . . . . . . . . . . . . . . 175, 176, 177, 178

DDR266A

Abstract: DDR333B EDD1232AABH-6B-E EDD1232AABH-7A-E
Contextual Info: DATA SHEET 128M bits DDR SDRAM EDD1232AABH 4M words x 32 bits Description Features The EDD1232AABH is a 128M bits DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data

Contextual Info: DATA SHEET 128M bits DDR SDRAM EDD1232AAFA-5 4M words x 32 bits, DDR400 Description Features The EDD1232AAFA is a 128M bits DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data

Contextual Info: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2508AETA 32M words x 8 bits EDD2516AETA (16M words × 16 bits) Specifications Features • Density: 256M bits • Organization ⎯ 8M words × 8 bits × 4 banks (EDD2508AETA) ⎯ 4M words × 16 bits × 4 banks (EDD2516AETA)

IC43R16320B

Abstract: DDR333 DDR400 IC43R16320B-6TL
Contextual Info: IS43R16320B IC43R16320B 512 Mb Double Data Rate Synchronous DRAM PRELIMINARY INFORMATION JUNE 2008 Features Specifications • Density: 512M bits • Organization ⎯ 8M words x 16 bits × 4 banks • Package: 66-pin plastic TSOP II ⎯ Lead-free (RoHS compliant)