AXI4 Search Results

AMBA AXI4 verilog code

Abstract: AMBA AXI specifications AMBA AXI4 pci to pci bridge verilog code Xilinx DS820 system verilog pcie microblaze state machine diagram for axi bridge Xilinx Virtex6 Design Kit 0X138
Contextual Info: LogiCORE IP AXI EP Bridge for PCI Express v1.01.a DS820 October 19, 2011 Product Specification Introduction t LogiCORE IP Facts Table The Advanced eXtensible Interface (AXI) Endpoint (EP) Bridge for PCI Express is an interface between the AXI4 bus and PCI Express. Definitions and

Contextual Info: LogiCORE IP SPI-4.2 v13.0 DS823 March 20, 2013 Product Specification Introduction LogiCORE IP Facts Core Specifics Device Family 1 Kintex-7, Virtex-7 Supported User Interface AXI4-Lite and AXI4-Stream Resources Used (2) Alignment Type FPGAs The Xilinx SPI-4.2 (PL4) core implements and is

XC6LX240T-FF1156

Abstract: virtex GTH AMBA AXI kintex 7 AMBA file write AXI verilog code aurora GTX virtex-7 XC6LX240T AMBA AXI4 verilog code 64B66B
Contextual Info: LogiCORE IP Aurora 64B/66B v7.1 DS815 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Aurora 64B/66B core supports the AMBA protocol AXI4-Stream user interface. It implements the Aurora 64B/66B protocol using the

SPARTAN-6 GTP

Abstract: msi g31 axi wrapper state machine diagram for axi bridge programmed fpga diagram and state machine axi 3 protocol XC6SLX4 DS820 MSIE PCIE interface
Contextual Info: LogiCORE IP AXI Bridge for PCI Express v1.03.a DS820 April 24, 2012 Product Specification Introduction t LogiCORE IP Facts Table The Advanced eXtensible Interface (AXI) Root Port/Endpoint (RP/EP) Bridge for PCI Express is an interface between the AXI4 and PCI Express.

virtex-7

Abstract: Aurora LX240T virtex7 vhdl coding for error correction and detection xilinx virtex-7 Spartan-6 LXT LX240T-FF1156 kintex 7
Contextual Info: LogiCORE IP Aurora 8B/10B v8.1 DS797 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Aurora 8B/10B core supports the AMBA protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the

g17g2

Abstract: state machine axi 3 protocol state machine diagram for axi bridge state machine axi DS712 G17G-2 AMBA AXI specifications 17256 XILINX
Contextual Info: LogiCORE IP AXI PLBv46 Bridge v2.02.a DS712 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The Advanced Microcontroller Bus Architecture (AMBA ) Advanced eXtensible Interface (AXI4) to Processor Local Bus (PLB v4.6) Bridge translates AXI

N25Q256

Abstract: WINBOND W25Q80 XC7K325TFFG900 XC6VLX130TFF1156 W25Q64VSFIG XC7K325T W25Q64vs axi4 DS843 W25Q80
Contextual Info: LogiCORE IP AXI Quad Serial Peripheral Interface AXI Quad SPI (v1.00a) DS843 October 19, 2011 Product Specification Introduction LogiCORE IP Facts The AXI Quad Serial Peripheral Interface connects the AXI4 interface to SPI slave devices that support the

Contextual Info: Video Broadcaster v1.00a DS880 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP Video Broadcaster core provides a flexible block for replicating a single inbound AXI4-Stream interface into multiple outbound

XC7K325TFFG900

Abstract: W25Q64VSFIG WINBOND W25Q80 SPARTAN 6 spi numonyx XPS ipic burst axi4 example Quad SPI N25Q256 NUMONYX xilinx spi XC7V285TFFG784-3 XC7K325T-ffg900
Contextual Info: LogiCORE IP AXI Quad Serial Peripheral Interface AXI Quad SPI (v2.00a) DS843 July 25, 2012 Product Specification Introduction LogiCORE IP Facts The AXI Quad SPI connects the AXI4 interface to those SPI slave devices that support Standard, Dual or Quad

zynq axi ethernet software example

Abstract: microblaze, SDK axi ethernet software example MM2S Xilinx ISE Design Suite 0x10111213 axi4
Contextual Info: LogiCORE IP AXI4-Stream FIFO v2.01a DS806 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI4-Stream FIFO core allows memory mapped access to a AXI4-Stream interface. The core can be used to interface to the AXI Ethernet without the complexity

xc6vlx130t-ff1156

Abstract: XILINX ipic axi
Contextual Info: LogiCORE IP AXI Serial Peripheral Interface AXI SPI (v1.02.a) DS742 January 18, 2012 Product Specification Introduction LogiCORE IP Facts The AXI Serial Peripheral Interface (SPI) connects to the Advanced eXtensible Interface (AXI4). This core provides a serial interface to SPI devices such as SPI

AMBA AXI4 stream specifications

Abstract: state machine axi 3 protocol state machine axi Xilinx ISE Design Suite
Contextual Info: LogiCORE IP AXI Slave Burst v1.00b DS769 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Slave Burst core provides an interface between the AXI4 memory-mapped interface and the IP interconnect interface. This core is designed

Contextual Info: LogiCORE IP AXI Quad Serial Peripheral Interface AXI Quad SPI v2.00a DS843 December 18, 2012 Product Specification Introduction LogiCORE IP Facts The AXI Quad SPI connects the AXI4 interface to those SPI slave devices that support Standard, Dual or Quad

XC6SLX45-2FGG484

Abstract: SPARTAN 6 xc6slx45 SLV64 spartan-6 XC6SLX45 DS765 XILINX ipic kintex 7 XC7K410TFFG676-3
Contextual Info: LogiCORE IP AXI4-Lite IPIF v1.01.a DS765 January 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM ) Advanced Microcontroller Bus Architecture (AMBA®) Advanced

ch249

Contextual Info: LogiCORE IP SPI-4.2 v12.2 DS823 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Core Specifics Device Family 1 Kintex-7, Virtex-7 Supported User Interface AXI4-Lite and AXI4-Stream Resources Used (2) Alignment Type FPGAs The Xilinx SPI-4.2 (PL4) core implements and is

Contextual Info: 66AK2E05, 66AK2E02 SPRS865B—June 2013—Revised January 2014 Multicore DSP+ARM KeyStone II System-on-Chip SoC 1 66AK2E05/02 Features and Description • ARM Cortex -A15 MPCore™ CorePac – Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz

Contextual Info: AM5K2E04, AM5K2E02 SPRS864B—June 2013—Revised January 2014 Multicore ARM KeyStone II System-on-Chip SoC 1 AM5K2E04/02 Features and Description • ARM Cortex -A15 MPCore™ CorePac – Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz – 4MB L2 Cache Memory Shared by all Cortex-A15

Contextual Info: AM5K2E04, AM5K2E02 SPRS864B—June 2013—Revised January 2014 Multicore ARM KeyStone II System-on-Chip SoC 1 AM5K2E04/02 Features and Description • ARM Cortex -A15 MPCore™ CorePac – Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz – 4MB L2 Cache Memory Shared by all Cortex-A15

P281 B01

Abstract: G187
Contextual Info: LogiCORE IP Processing System 7 v4.02a DS871 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The Processing System 7 IP is the software interface around the Zynq Processing System. The Zynq -7000 family consists of an system-on-chip (SoC) style

Contextual Info: LogiCORE IP AXI Interconnect v1.06.a DS768 December 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AXI

SPRS836D

Contextual Info: TCI6638K2K SPRS836D—February 2012—Revised October 2013 Multicore DSP+ARM KeyStone II System-on-Chip SoC 1 TCI6638K2K Features and Description 1.1 Features • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With – 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point DSP Core

Contextual Info: AM5K2E04/02 Multicore ARM KeyStone II System-on-Chip SoC Data Manual PRODUCT PREVIEW information applies to products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products

AMBA AXI4 verilog code

Abstract: ZYNQ-7000 BFM 20/ZYNQ-7000 BFM
Contextual Info: LogiCORE IP AXI Bus Functional Models v3.00.a DS824 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP AXI Bus Functional Models (BFMs), developed for Xilinx by Cadence Design Systems, support the simulation of

XC7K325T-ffg900

Abstract: XC7K325TFFG900 VX690T
Contextual Info: Vivado Design Suite User Guide Release Notes, Installation, and Licensing UG973 v2013.2 June 19, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum