BG256 Search Results

Contextual Info: Product Obsolete/Under Obsolescence R XC4000XLA Family Field Programmable Gate Arrays Package Pinouts XC4013XLA Pinout Table XC4013XLA Pinout Table Continued XC4013XLA Pinout Table PAD NAME PQ160 PQ208 PQ240 I/O – – P21 BG256 H1 PAD NAME PQ160 PQ208

BG256

Contextual Info: R Plastic BGA BG256 Package PK018 (v1.0) June 1, 2000 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

BG256

Abstract: BG352 352-LEAD
Contextual Info: Package Diagrams Ball Grid Array Packages 119-Lead FBGA 14 x 22 x 2.4 mm BG119 51-85115 1 Package Diagrams 256-Lead Ball Grid Array (27 x 27 x 2.33 mm) BG256 51-85097 2 Package Diagrams 352-Lead Ball Grid Array (35 x 35 x 2.33 mm) BG352 51-85103 3

Diagrams

Abstract: 5185143 BG-272 mold cap BG256 BG352 BG-209 Package Diagrams 14X22
Contextual Info: Package Diagrams Ball Grid Array Packages 119-Lead PBGA 14 x 22 x 2.4 mm BG119 51-85115-*A 1 Package Diagrams 209-Lead PBGA (14 x 22 x 2.20 mm) BG209 51-85143-*A 2 Package Diagrams 256-Lead PBGA (27 x 27 x 2.33 mm) BG256 51-85097-*A 3 Package Diagrams 272-Lead Ball Grid Array (27 x 27 x 2.33 mm) BG272

BGG256

Abstract: PK018 BG256
Contextual Info: R Plastic BGA BG256/BGG256 Package PK018 (v1.3) March 19, 2007 256-BALL PLASTIC BGA (BG256/BGG256) 2001, 2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.

Contextual Info: R Plastic BGA BG256 Package PK018 (v1.1) April 6, 2001 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

BG256

Contextual Info: BGA Packages - BG256 July 2, 1998 Version 1.3 10-33

BG256

Contextual Info: BGA Packages - BG256 November 13, 1997 Version 1.2 10-33

BG-272

Abstract: 5185130
Contextual Info: Package Diagrams Ball Grid Array Packages 119-Lead FBGA 14 x 22 x 2.4 mm BG119 51-85115 1 Package Diagrams 256-Lead Ball Grid Array (27 x 27 x 2.33 mm) BG256 51-85097 2 Package Diagrams 272-Lead Ball Grid Array (27 x 27 x 2.33 mm) BG272 51-85130 3 Package Diagrams

BG256

Contextual Info: Package Diagram Ball Grid Array Packages 256-Lead Ball Grid Array 27 x 27 x 2.33 mm BG256 51-85097 1

n20s

Abstract: A144 BG256 IEEE1164 Military Plastic pASIC 3 Family 256
Contextual Info: 3T PRELIMINARY CYPRESS Ultra38007 UltraLogic Very High Speed 7K Gate CMOS FPGA Features — Minimum Iol and Ioh 24 mA Flexible logic cell architecture — Wide fan-in up to 16 input gates — Multiple outputs in each cell — Very low cell propagation delay

CY37384

Abstract: CY37384V L0651
Contextual Info: = j— PRELIMINARY T. # CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Fully Routable with 100% Logic Utilization Features — JTAG-compliant on-board programming The CY37384V is designed with a robust routing architecture which allows utilization of the entire device with a fixed pinout.

transistor bl p89

Abstract: bl p74 transistor J955 XC4000 XC4000A XC4000D XC4000E XC4000EX XC4000H p180 g8
Contextual Info: book XC4000E and XC4000X Series Field Programmable Gate Arrays R January 29, 1999 Version 1.5 6* XC4000E and XC4000X Series Features Note: XC4000 Series devices described in this data sheet include the XC4000E family and XC4000X Series. XC4000X Series devices described in this data sheet

CY37384

Abstract: CY37384V
Contextual Info: PRELIMINARY CY37384 UltraLogic 384-Macrocell ISR™ CPLD — tS = 5.5 ns Features • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • • • • • — Design changes don’t cause pinout changes

FPGA Virtex 6 pin configuration

Abstract: Virtex CS144 TQ144 XCV100 XCV150 XCV200 XCV300 XCV50 xapp151
Contextual Info: Virtex 2.5 V Field Programmable Gate Arrays R 3 Architectural Description The output buffer and all of the IOB control signals have independent polarity controls. VersaRing The Virtex architecture also includes the following circuits that connect to the GRM.

XC9572XL

Abstract: PC44 VQ44 XC9500 XC9500XL XC95144XL XC95288XL XC9536XL XC95288XL pinout
Contextual Info: k XC9500XL High-Performance CPLD Family Data Sheet R DS054 v2.5 May 22, 2009 Product Specification Features • • Optimized for high-performance 3.3V systems - 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz - Small footprint packages including VQFPs, TQFPs

LCMXO2-1200HC-4TG100C

Abstract: LCMXO2-256HC-4TG100I LCMXO2-1200 tn1200 lcmxo2 LCMXO2-1200HC-4TG100 LCMXO2-2000 LCMXO2-7000 MachXO2-1200 LCMXO2-4000HC
Contextual Info: MachXO2 Family Handbook HB1010 Version 01.0, November 2010 MachXO2 Family Handbook Table of Contents November 2010 Section I. MachXO2 Family Data Sheet Introduction Features . 1-1

AAAG 6 pin ic

Abstract: n208
Contextual Info: CYPRESS Features PRELIMINARY UltraLogic Very High Speed 7K Gate CMOS FPGA — Minimum Iol and Ioh ° f 24 mA • Flexible logic cell architecture — Wide fan-in up to 16 input gates — Multiple outputs in each cell — Very low cell propagation delay

Contextual Info: QPRO XQ4000XL Serles QML flX IU N X High-Reliablllty Field Programmable Gate Arrays May 19, 1998 Version 1.0 XG4QQQX Series Features • • • • • • • • • • • • • • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing)

Contextual Info: • ■ J ^ m n r n n PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 256 macrocells in sixteen logic blocks • In-System Reprogram mable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: HXILINX Virtex 2,5 ¥ Field Programmable Gate Arrays N ovem ber 9, 1998 Version 1.1 - AD VAN C E P roduct S pecification Features • • • • • • Fast, high-density Field-P rogram m able Gate Arrays - D ensities from 50 k to 1M system gates - System perform ance up to 200 MHz

Contextual Info: flX IU N X Spartan and S p artan X l Families Field Programmable Gate Arrays September 28, 1998 Version 1.2 Preliminary Product Specification Introduction • System level features - Available in both 5.0 Volt and 3.3 Volt versions - On-chip SelectRAM memory

Contextual Info: Spartan and SpartanXL Families Field Programmable Gate Arrays £ XILINX January 6 , 1999 Version 1.4 Prelim inary Product Specification Introduction • The S partan Series is the first high-volum e production FPGA solution to deliver all the key requirem ents for ASIC

qfn 3x3 tray dimension

Abstract: XCDAISY BFG95 XC5VLX330T-1FF1738I pcb footprint FS48, and FSG48 WS609 jedec so8 Wire bond gap XC3S400AN-4FG400I FFG676 XC4VLX25 cmos 668 fcbga
Contextual Info: Device Package User Guide [Guide Subtitle] [optional] UG112 v3.5 November 6, 2009 [optional] R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the