BURST BUS MODE Search Results

Motorola MPC556

Abstract: MPC556 Motorola 417 0C00 1C00 MPC555 0x80E0 branch conditional unconditional instruction
Contextual Info: SECTION 4 BURST BUFFER The burst buffer module consists of the burst buffer controller BBC and the instruction memory protection unit (IMPU). The BBC delivers the RCPU instruction fetch accesses from the instruction bus onto the U-bus. It utilizes the full U-bus pipeline and a special page access attribute in order

Motorola MPC556

Abstract: 0C00 1C00 MPC555 MPC556 Motorola 417 "Huffman coding" branch conditional unconditional instruction
Contextual Info: SECTION 4 BURST BUFFER The burst buffer module consists of the burst buffer controller BBC and the instruction memory protection unit (IMPU). The BBC delivers the RCPU instruction fetch accesses from the instruction bus onto the U-bus. It utilizes the full U-bus pipeline and a special page access attribute in order

0x802c

Abstract: 0x00E00 SRR10 0x8074 0C00 1C00 MPC555 0x8070 0x01d00
Contextual Info: SECTION 4 BURST BUFFER The burst buffer module consists of the burst buffer controller BBC and the instruction memory protection unit (IMPU). The BBC delivers the RCPU instruction fetch accesses from the instruction bus onto the U-bus. It utilizes the full U-bus pipeline and a special page access attribute in order

diode BBC

Abstract: 0x80E0 0C00 1C00 MPC555
Contextual Info: SECTION 4 BURST BUFFER The burst buffer module consists of the burst buffer controller BBC and the instruction memory protection unit (IMPU). The BBC delivers the RCPU instruction fetch accesses from the instruction bus onto the U-bus. It utilizes the full U-bus pipeline and a special page access attribute in order

MCF5206

Contextual Info: SECTION 6 BUS OPERATION The MCF5206 bus interface supports synchronous data transfers that can be terminated synchronously or asynchronously and burst or burst-inhibited between the MCF5206 and other devices in the system. This section describes the function of the bus, the signals that

PC107A

Abstract: microprocessor PC107
Contextual Info: PC107A PCI Bridge Memory Controller Datasheet Features • Processor Bus Frequency up to 100 MHz • 64- or 32-bit Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1

4082

Abstract: c 4082 PBSRAM ci 4082
Contextual Info: PRELIMINARY IDT7MBV4150 IDT7MBV4151 IDT7MBV4152 128K x 64/256K x 72 SYNCHRONOUS PIPELINED BURST SRAM 256K x 72 BURST ZBT SRAM MODULE FAMILY FEATURES: DESCRIPTION: • Pin compatible module family for pipelined burst SRAM and pipelined burst zero bus turnaround ZBT™ SRAM

M68040

Abstract: MC68EC040 MC68LC040 BB 36 931 937 motorola
Contextual Info: INDEX -A - Bus Cycle, 7-29, 7-35, 9-20 BSDL Description, 6-15 Access Control Unit, 1-2, B-4, B-5 Buffer Selection, 7-69 Access Control Unit Register, B-5; Burst Mode Operations, 4-3, 4-11, 5-9 Field Definitions, B -6-B -7 Burst Bus Cycles, s e e Bus Cycles

T25 4 F8

Abstract: PC7400 ATMEL 744 MPC107 PC107A PCX107A
Contextual Info: Features • Processor Bus Frequency up to 100 MHz • 64- or 32-bit Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operates up to 66 MHz/5.0V Compatible

MPC107

Abstract: PC107A PC7400 atmel 458
Contextual Info: Features • Processor Bus Frequency up to 100 MHz • 64- or 32-bit Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operates up to 66 MHz/5.0V Compatible

MPC107

Abstract: PC107A PC7400
Contextual Info: Features • Processor Bus Frequency up to 100 MHz • 64- or 32-bit Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operates up to 66 MHz/5.0V Compatible

TMs 1122

Contextual Info: Features • Processor Bus Frequency up to 100 MHz • 64- or 32-bit Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operates up to 66 MHz/5.0V Compatible

a23 862-1

Abstract: T25 4 h5 ATMEL 744 W6 13A Diode atmel 718 atmel 819 diode t25 4 E5 diode t25 4 L5 IN5820 military standard mpc107
Contextual Info: Features • Processor Bus Frequency up to 100 MHz • 64- or 32-bit Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operates up to 66 MHz/5.0V Compatible

MOSYS

Abstract: MC8051M36 MC8051M36L-7R5VI 1.8V SRAM
Contextual Info: ♦ MC8051M36 36-Mbit: 1Mx36 M o Sys * Symmetric Pipelined Burst SRAM • High Performance • 133-200MHz Speed grades • 3-1-1-1 Burst Read • 3-1-1-1 Burst Write • 3-1-1-1-1-1-1-1. pipelined operation lu • Symm etric Pipeline • No bus turnaround latency allowing 100% bus efficiency

diode t25 4 B9

Abstract: diode t25 4 L5 g24 motorola module datasheet la 7680 T25 4 h5 AD14 MPC107 PC107A PC7400
Contextual Info: Features • Processor Bus Frequency up to 100 MHz • 64-bit or 32 bits Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operates up to 66 MHz/5.0V Compatible

PC7400

Contextual Info: Features H Processor bus frequency up to 100 MHz. H 64-bit or 32 bits data bus and 32-bit address bus. H Provides support for either asynchronous SRAM, burst SRAM, or pipelined burst SRAM. H Compliant with PCI specification, revision 2.1. H PCI interface operates up to 66 MHz/5.0 Volt compatible.

MPC107

Abstract: PC107A PC7400
Contextual Info: Features H Processor bus frequency up to 100 MHz. H 64-bit or 32 bits data bus and 32-bit address bus. H Provides support for either asynchronous SRAM, burst SRAM, or pipelined burst SRAM. H Compliant with PCI specification, revision 2.1. H PCI interface operates up to 66 MHz/5.0 Volt compatible.

Contextual Info: Features H Processor bus frequency up to 100 MHz. H 64-bit or 32 bits data bus and 32-bit address bus. H Provides support for either asynchronous SRAM, burst SRAM, or pipelined burst SRAM. H Compliant with PCI specification, revision 2.1. H PCI interface operates up to 66 MHz/5.0 Volt compatible.

i960 sb

Abstract: Intel i960 features intel i960 RISC intel microprocessor 32 bit pin diagram i960 mc errata Intel i960 architecture intel i960 80960SB embedded microprocessors
Contextual Info: 272234-004.qxd 12/26/00 9:59 AM Page 1 product brief i960 SA/SB 32-Bit Embedded Microprocessors with a 16-Bit Burst Data Bus Product Highlights developer.intel.com • High-Performance 32-bit Embedded Architecture ■ High-Speed 16-bit Burst Data Bus ■

SRAM 256K

Contextual Info: 128K x 64/256K x 72 Synchronous Pipelined Burst SRAM 256K x 72 Burst ZBT SRAM Module Family Features ◆ Description Pin compatible module family for pipelined burst SRAM and pipelined burst zero bus turnaround ZBT™ SRAM Low profile 160-lead AMP Free Height Surface Mount Boardto-Board Connector family (5mm-8mm plug options)

A23 1101 01A

Contextual Info: PRELIMINARY « ¿ F CY82C599 CY PRESS Intelligent PCI Bus Controller Features Supports 4 PCI Masters • Provides an interface between the PCI Local Bus and the CPU bus • PCI Bus Rev. 2.0 compliant Supports burst mode PCI accesses to memory space • Supports Intel 486DX, 486DX2,

AN-630

Abstract: C1995 NS32532 NS32GX AN630 NS32GX32
Contextual Info: National Semiconductor Application Note 630 Zeev Bikowsky Aharon Ostrer July 1989 INTRODUCTION The NS32GX32 burst mode is a mechanism for increasing the bus transfer rate Implementing the burst mode enables the CPU to read 4 double words in 5 cycles During nonburst

AM79C900

Abstract: 32 bit risc processor using vhdl AM79C940 R3051 R3052 R3081
Contextual Info: Simulation Tools / Models Papillon Research Corp. VHDL MODELS for the R3051 family of RISC Processors Standard Features ❏ Full bus mastership/arbitration ❏ Single reads/writes ❏ Burst reads ❏ Page detect for burst pin ❏ File defined timing ❏ Complete timing checks

intel i960 RISC

Abstract: ZN1331 ZIETNET ZEITNET
Contextual Info: ATM ZIETNET, INC. ZATM EISA Bus ATM Adapter High-Performance • Built-In DMA Bus Mastering Capabilities Reduce CPU Overhead ■ 32-Bit Bus Interface and Burst Mode Capabilities Allow Maximum Transfer Rates For Greater Speed and Efficiency ■ 16 Traffic Shapers Allow For