CDCM1802RGTR Search Results

CDCM1802RGTR Result Highlights (1)

Part	ECAD Model	Manufacturer	Description	Download	Buy
CDCM1802RGTR		Texas Instruments	Clock Buffer w/Programmable Divider, LVPECL I/O + addl LVCMOS output 16-VQFN -40 to 85

CDCM1802RGTR Datasheets (6)

Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
CDCM1802RGTR		Texas Instruments	CDCM1802 - Clock Buffer w/Programmable Divider, LVPECL I/O + addl LVCMOS output 16-QFN -40 to 85	Original	PDF	553.19KB	25
CDCM1802RGTR		Texas Instruments	Logic and Timing, Clock Buffer w/Programmable Divider, LVPECL I/O + addl LVCMOS output, Tape and Reel	Original	PDF	586.1KB	20
CDCM1802RGTR		Texas Instruments	Clock Buffer w/Programmable Divider, LVPECL I/O + addl LVCMOS output 16-QFN -40 to 85	Original	PDF	833.74KB	24
CDCM1802RGTRG4		Texas Instruments	CDCM1802 - Clock Buffer w/Programmable Divider, LVPECL I/O + addl LVCMOS output 16-QFN -40 to 85	Original	PDF	553.19KB	25
CDCM1802RGTRG4		Texas Instruments	Clock Buffer w/Programmable Divider, LVPECL I/O + addl LVCMOS output	Original	PDF	810.79KB	23
CDCM1802RGTRG4		Texas Instruments	Clock Buffer w/Programmable Divider, LVPECL I/O + addl LVCMOS output 16-QFN -40 to 85	Original	PDF	833.74KB	24

CDCM1802RGTR Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
SLUA271 Abstract: QFN PACKAGE thermal resistance JESD51-7 QFN PACKAGE Junction to PCB thermal resistance CDCM1802 CDCM1802RGTR SCAA062 SLUA Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL	Original	CDCM1802 SCAS759 800-MHz 200-MHz SLUA271 QFN PACKAGE thermal resistance JESD51-7 QFN PACKAGE Junction to PCB thermal resistance CDCM1802 CDCM1802RGTR SCAA062 SLUA	PDF
Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL	Original	CDCM1802 SCAS759 800-MHz 200-MHz 16-Pin	PDF
Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759A − APRIL 2004 − JULY 2009 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6	Original	CDCM1802 SCAS759A 800-MHz 200-MHz 16-Pin	PDF
Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL	Original	CDCM1802 SCAS759 800-MHz 200-MHz 16-Pin	PDF
Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL	Original	CDCM1802 SCAS759 800-MHz 200-MHz 16-Pin CDCM1802: /USER-SHARED/TXIIS18762-1	PDF
SLUA271 Abstract: CDCM1802 CDCM1802RGTR SCAA062 Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL	Original	CDCM1802 SCAS759 800-MHz 200-MHz SLUA271 CDCM1802 CDCM1802RGTR SCAA062	PDF
SLUA271 Abstract: SCAA062 CDCM1802 CDCM1802RGTR Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL	Original	CDCM1802 SCAS759 800-MHz 200-MHz SLUA271 SCAA062 CDCM1802 CDCM1802RGTR	PDF
Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL	Original	CDCM1802 SCAS759 800-MHz 200-MHz 16-Pin	PDF
CDCM1802 Abstract: CDCM1802RGTR SCAA062 SLUA271 Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL	Original	CDCM1802 SCAS759 800-MHz 200-MHz CDCM1802 CDCM1802RGTR SCAA062 SLUA271	PDF
CDCM1802 Abstract: CDCM1802RGTR SCAA062 SLUA271 Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL	Original	CDCM1802 SCAS759 800-MHz 200-MHz CDCM1802 CDCM1802RGTR SCAA062 SLUA271	PDF
Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL	Original	CDCM1802 SCAS759 800-MHz 200-MHz 16-Pin	PDF
Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL	Original	CDCM1802 SCAS759 800-MHz 200-MHz 16-Pin	PDF
Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL	Original	CDCM1802 SCAS759 800-MHz 200-MHz 16-Pin	PDF
Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759A − APRIL 2004 − JULY 2009 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6	Original	CDCM1802 SCAS759A 800-MHz 200-MHz 16-Pin	PDF

Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL	Original	CDCM1802 SCAS759 800-MHz 200-MHz 16-Pin	PDF
SLUA271 Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL	Original	CDCM1802 SCAS759 800-MHz 200-MHz 16-Pin MSP430 S325F5351WYYRQC1JAVR3KQ CDCM1802RGT SLUA271	PDF
Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL	Original	CDCM1802 SCAS759 800-MHz 200-MHz 16-Pin	PDF
Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759A − APRIL 2004 − JULY 2009 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6	Original	CDCM1802 SCAS759A 800-MHz 200-MHz	PDF