CLASSIC EPLD FAMILY Search Results

Contextual Info: ÆÎIMSSv Classic Contents Classic EPLD Family Data Sheet Features. 745 General

EP900ILC-50

Abstract: EP900IPC-50 EP900IDC-50 EP900IDC50 altera ep900 EP900IPC60 altera ep900i ep900ipc-60 intel 5C090 altera speed grade
Contextual Info: EP900I /ANlIs.nyA\ Classic EPLD March 1995, ver. 2 Data Sheet Supplement This data sheet supplement should be used together with the Classic Family Data Sheet. Features □ □ □ □ □ Formerly Intel's 5C090 device High-performance, 24-macrocell Classic EPLD

ep22v10

Abstract: EP1810 jedec
Contextual Info: Classic C o n te n ts March 1995 Classic EPLD Family Features. 333 General

Contextual Info: Classic C o n te n ts Classic EPLD Family Data Sheet Features. 421 General Description. 422

Contextual Info: ¿sonisi Classic Contents J u n e 1996 Classic EPLD Family Data Sheet F eatures. 349 General Description. 350

Contextual Info: Classic EPLD Family June 1996, ver. 3 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ Table 1. Classic Device Features Feature EP1810 900 300 450 16 24 48 Maximum user I/O pins 22 38 64 tp D n s 10 12 20 100 76.9 50 f CNT A-DS-CLASSIC-03 EP910 &

sts37e

Abstract: EP600IPC-45 EP600IDC-45 EP600IPC-55 altera ep610 5c060 EP600IDM883B55 ep600ilc ep600i EP600IDC45
Contextual Info: EP600I Classic EPLD Data Sheet Supplement March 1995, ver. 2 This data sheet supplement should be used together with the Classic Family Data Sheet and the Altera Device Package Outlines Data Sheet in the current data book. Features ^ □ □ □ □ □ Formerly Intel's 5C060 device

EP600IPC-45

Abstract: 5962-8686401la ep600i Altera Classic EPLDs altera ep610
Contextual Info: ANbi^n^ EP600I Classic EPLD Data Sheet Supplement March 1995, ver. 2 This data sheet supplement should be used together with the Classic Family Data Sheet and the Altera Device Package Outlines Data Sheet in the current data book. Features ^ □ □ □ □

FC SUFFIX altera

Contextual Info: Classic EPLD Family Data Sheet M arch 1995, ver. 2 Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ Table 1. Classic Device Features Feature EP22V10 EP22V10E EPB10 EP610T EP610I EP910 EP910T EP910I EP1810 EP1810T Available gates 400 600 600 900 900 1,800 Usable gates

Contextual Info: EP610 EPLD Features High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD as low as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins

Signal Path Designer

Contextual Info: Classic EPLD Family J a n u a ry 1998. ver. Features Data Sheet 4 * • ■ ■ ■ ■ ■ ■ ■ Table 1. Classic Device Features EP610 EP610I EP910 EP910I EP1810 300 450 900 Macrocells 16 24 48 Maximum user I/O pins 22 38 64 Feature Usable gates Altera Corporation

C2657

Abstract: EPI810 K102-8 EP181B
Contextual Info: EP1810 EPLD Features • ■ ■ ■ ■ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD as fast as 20 ns - Counter frequencies of up to 50 MHz - Pipelined data rates of up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs

EP610-30

Abstract: EP610-35 EP610-25 EP610 EP610-15 EP610-20 EP6101-10 EP610I
Contextual Info: EP610 EPLD Features * • ■ ■ ■ ■ High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tP D as fast as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs

fxz 556

Abstract: EP6101-10 EP610 pipelined adder EP610-Z5 EP610-30 EP610-35 EP610-25 EP610-15 EP610-20
Contextual Info: EP6 1 0 EPLD High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD as fast as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins

altera ep900i

Abstract: IC MSI ADDER
Contextual Info: EP910 EPLD Features High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD as low as 12 ns Counter frequencies of up to 76.9 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs EP910, EP910I, and EP900I devices that are pin-, function, and

Contextual Info: EP1810 EPLD Features • ■ ■ ■ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with t P D as fast as 20 ns Counter frequencies of up to 50 MHz Pipelined data rates of up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs

ep910 programmer

Abstract: EP610 programmer EPLD EP610-25 EP1810 EP610-15 EP610-20 EP610-30 EP910 K925
Contextual Info: Classic EPLD Family May 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with non-volatile EPROM configuration elements

ep600i

Abstract: EP1800I EP610ILI-12 altera ep610 altera EP1810 EP1800 altera ep900i
Contextual Info: Classic EPLD Family June 1996, ver. 3 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of up to 900 usable gates see Table 1 Device erasure and reprogramming with advanced, non-volatile EPROM configuration elements

EP910dm

Abstract: EP910PC-30 EP910DC-40 EP1810LC-35 EP1810LC-20 EP610PC-15 Programming EP610DI-30 EP910JI-35 EP610IDC25 EP610SC-15
Contextual Info: Classic EPLD Family May 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with non-volatile EPROM configuration elements

Altera EP1810

Abstract: EP1810 EP600I EP610 EP610-15 EP610-20 EP910 EP610 "pin compatible"
Contextual Info: Classic EPLD Family June 1996, ver. 3 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of up to 900 usable gates see Table 1 Device erasure and reprogramming with advanced, non-volatile EPROM configuration elements

Contextual Info: Classic EPLD Family January 1998, ver. 4 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with advanced, non-volatile EPROM configuration elements

ep910 programmer

Abstract: EP610 EP610-15 48-macrocell EP1810 EP610-20 EP610-25 EP610-30 EP910 ep610 application
Contextual Info: Classic EPLD Family May 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with non-volatile EPROM configuration elements

Signal Path Designer

Contextual Info: Classic EPLD Family M ay 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family w ith logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogram m ing w ith non-volatile EPROM configuration elements

EP610

Abstract: ep910 programmer TI EP610 EP610-25 EP1810 EP910 ALTERA MAX 5000 programming EP6101-10
Contextual Info: Classic EPLD Family January 1998. ver. 4 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family w ith logic densities of 300 to 900 usable gates see Fable 1 Device erasure and reprogram m ing w ith advanced, non-volatile EPROM configuration elements