CONTROL LOGIC 24 LAGS Search Results

64k fifo

Contextual Info: QS7306 64K x 4 Ultra Deep FIFO Memory Q QS73oe ,nfoArm\ n FEATURES/BENEFITS • • • • • 64Kx4 Ultra Deep FIFO Reversible A to B or B to A OE control pin 1/2,1/4,1/16,1/32 status (lags Directly cascades with another UD FIFO • • • • 50 MHz clocked interface

Contextual Info: Preliminary Information JB TE X A R XR16C850 UART WITH 128-BYTE FIFO’s AND INFRARED IrDA ENCODER/DECODER PLCC Package GENERAL DESCRIPTION The XR16C850*1 (850) is a universal asynchronous receiver and transm itter (UART) and is pin compatible with the ST16C650A UART. The 850 is an enhanced

FIFO memory

Abstract: ST16C650A
Contextual Info: áç XR16L651 PRELIMINARY 2.5V, 3.3V AND 5V LOW POWER UART WITH 32-BYTE FIFO MAY 2001 REV. P1.0.3 GENERAL DESCRIPTION FEATURES The XR16L6511 651 is a 2.5V, 3.3V and 5V Universal Asynchronous Receiver and Transmitter (UART) with 5V tolerant inputs. This new device supports Intel

mcr 5102

Abstract: TDA 4844 ST16C650A 16C450 16C550 16L651 ST16C580 XR16L651 XR16L651CM IT71
Contextual Info: áç XR16L651 2.5V, 3.3V AND 5V LOW POWER UART WITH 32-BYTE FIFO DECEMBER 2001 REV. 1.1.1 GENERAL DESCRIPTION FEATURES The XR16L6511 651 is a 2.5V, 3.3V and 5V Universal Asynchronous Receiver and Transmitter (UART) with 5V tolerant inputs. This new device supports Intel

ST16C650A

Contextual Info: áç XR16L651 PRELIMINARY 2.5V, 3.3V AND 5V LOW POWER UART WITH 32-BYTE FIFO APRIL 2001 REV. P1.0.2 GENERAL DESCRIPTION FEATURES The XR16L6511 651 is a 2.5V, 3.3V and 5V Universal Asynchronous Receiver and Transmitter (UART) with 5V tolerant inputs. This new device supports Intel

mcr 5102

Contextual Info: áç XR16L651 2.5V, 3.3V AND 5V LOW POWER UART WITH 32-BYTE FIFO MAY 2001 REV. 1.1.0 GENERAL DESCRIPTION FEATURES The XR16L6511 651 is a 2.5V, 3.3V and 5V Universal Asynchronous Receiver and Transmitter (UART) with 5V tolerant inputs. This new device supports Intel

ST16C650A

Contextual Info: áç XR16L651 PRELIMINARY 2.5V, 3.3V AND 5V LOW POWER UART WITH 32-BYTE FIFO MARCH 2001 REV. P1.0.1 GENERAL DESCRIPTION FEATURES The XR16L6511 651 is a 2.5V, 3.3V and 5V Universal Asynchronous Receiver and Transmitter (UART) with 5V tolerant inputs. This new device supports Intel

ST16C650A

Contextual Info: áç XR16L651 PRELIMINARY 2.5V, 3.3V AND 5V LOW POWER UART WITH 32-BYTE FIFO JANUARY 2001 REV. P1.0.0 GENERAL DESCRIPTION FEATURES The XR16L6511 651 is a 2.5V, 3.3V and 5V Universal Asynchronous Receiver and Transmitter (UART) with 5V tolerant inputs. This new device supports Intel

x0606

Abstract: STS-1100 RISCwatch ppc jtag
Contextual Info:  IBM Power Network Processor, Resource Manager PNr2.7 Databook Preliminary  Copyright and Disclaimer  Copyright International Business Machines Corporation 1999, 2000 All Rights Reserved Printed in the United States of America July 2000 The following are trademarks of International Business Machines Corporation in the United States, or other countries,

Contextual Info: L4C381 16-bit Cascadable ALU FEATURES □ High-Speed 15ns , Low Power 16-bit Cascadable ALU □ Implements Add, Subtract, Accu­ mulate, Two’s Complement, Pass, and Logic Operations □ All Registers Have a Bypass Path for Complete Flexibility □ DESC SMD No. 5962-89959

L4C381EC-40

Contextual Info: L4C381 16-bit Cascadable ALU FEATURES □ High-Speed 15ns , Low Power 16-bit Cascadable ALU □ Implements Add, Subtract, Accu­ mulate, Two's Complement, Pass, and Logic Operations □ All Registers Have a Bypass Path for Complete Flexibility □ DESC SMD No. 5962-89959

Contextual Info: PMC-Sierra, Inc. PM6344 EQUAD STANDARD PRODUCT ISSUE 5 QUADRUPLE E1 FRAMER :2 6: 24 AM PMC-951013 ay fe fo n Mo nd EQUAD ,0 3M ay ,2 00 4 11 PM6344 Do wn lo ad ed by ef we fe fe fo fe QUADRUPLE E1 FRAMER ISSUE 5: JUNE 1998 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

"176-pin" conexant

Abstract: CX25800 6h16 h20xxx rasco PLUS m DSH-201233A
Contextual Info: CX25800 PCI Video Decoder with Mono Audio Input Data Sheet DSH-201233A July 2007 Ordering Information Model Number Description CX25800 Package Operating Temperature 176-pin LQFP 0 to +70 oC Minimum Order Quantities Revision History Revision Date A July 2, 2007

200H

Abstract: PM4388 337H
Contextual Info: PM4388 TOCTL DATA SHEET PMC-960840 ISSUE 4 OCTAL T1 FRAMER PM4388 TOCTL OCTAL T1 FRAMER DATA SHEET ISSUE 4: DECEMBER 1997 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PM4388 TOCTL DATA SHEET PMC-960840 ISSUE 4 OCTAL T1 FRAMER

451H

Abstract: 339H 200H PM4388
Contextual Info: PM4388 TOCTL DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER PM4388 TOCTL OCTAL T1 FRAMER DATASHEET ISSUE 5: NOVEMBER 1998 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PM4388 TOCTL DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER

Contextual Info: L p fjfô L4C381 devicesincorporated 16 -bit Cdscddsbls ALU DESCRIPTION FEATURES □ H igh-Speed 15ns , Low Pow er 16-bit Cascadable ALU □ Im plem ents A dd, Subtract, A ccu­ m ulate, T w o's Com plem ent, Pass, and Logic O perations □ All Registers H ave a Bypass Path

Panduit

Abstract: socket AM2 pinout AM2 CPU pinout j29 pinout C130 CH30 LM339 R117 R118 KE-25
Contextual Info: VMIVME-1183 32-Channel P2 Digital Input Board with Change-of-State Interrupts, Sequenceof-Events and Built-in-Test Product Manual 256 880-0444 w 12090 South Memorial Parkway Huntsville, Alabama 35803-3308, USA (800) 322-3616 w Fax: (256) 882-0859 500-001183-000 Rev. A

Contextual Info: Q C S A M S U N G m.m Semiconductor - KM75C02A CMOS PARALLEL FIRST-IN/FIRST-OUT FIFO Preliminary FEATURES DESCRIPTION • The KM75C02A is a dual port memory that implements a special First-in, First-Out algorithm that loads and emp­ ties data on a first-in, first-out basis. Full and empty lags

LF44xx

Abstract: LF4460 full hd video processor LF4415 "Frame rate conversion"
Contextual Info: LF4460 LF4430 LF4415 PRELIMINARY Video Memory / FIFO FRAME MEMORY Features Selectable I/O VDD = 1.8V, 2.5V, 3.3V Selectable Core VDD = 1.8V, 2.5V, 3.3V 172 ball FBGA package 15 x 15 x 1.4mm Depth expansion is supported for Multi-frame HDTV, Multiframe SDTV, and other formats:

cs5460 adc code example

Abstract: 1000w power AMPLIFIER pcb circuit layout CS5460 1000w power amplifier circuit diagram application notes CS5460 adc cs5460 ups circuit schematic diagram 1000w CDB5460 CS5460A CS5460-BS
Contextual Info: CS5460 Single Phase Bi-Directional Power/Energy IC Features Description l Energy The CS5460 is a highly integrated ∆Σ Analog-to-Digital Converter ADC which combines two ∆Σ ADCs, high speed power calculation functions, and a serial interface on a single chip. It is designed to accurately measure

Contextual Info: PM4388 TOCTL DATA SHEET ISSUE 5 OCTAL T1 FRAMER :3 1: 10 AM PMC-960840 ay fe fo n Mo nd TOCTL ,0 3M ay ,2 00 4 11 PM4388 DATASHEET Do wn lo ad ed by ef we fe fe fo fe OCTAL T1 FRAMER ISSUE 5: NOVEMBER 1998 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

PM438S

Abstract: PM438B
Contextual Info: PMC-Sierra, Inc. PM4388 TOCTL DATA SHEET PMC-960840 ISSUE 4 OCTAL T1 FRAMER PM4388 TOCTL OCTAL T1 FRAMER DATA SHEET ISSUE 4: DECEMBER 1997 PROPRIETARY ANO CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE r i V I V — P M C ' S ierra’ ln a

be01a

Abstract: TJA11
Contextual Info: L4C381 16-bit Cascadable ALU D E V IC E S IN C O R P O R A T E D FEATURES □ H igh-Speed 15ns , Low Pow er 16-bit C ascadable ALU □ Im plem ents A dd, Subtract, A ccu­ m ulate, T w o's C om plem ent, Pass, and Logic O perations □ All R egisters H ave a Bypass Path

Contextual Info: L4C381 16-bit Cascadable ALU □ FV IC E S IN C O R P Q R A T F D DESCRIPTION FEATURES The L4C381 is a flexible, high speed, cascadable 16-bit Arithmetic and Logic Unit. It combines four 381-type 4-bit ALUs, a look-ahead carry generator, and miscellaneous interface