CY7B9920 Search Results

CY7B9910

Abstract: CY7B9920
Contextual Info: fax id: 3516 CY7B9910 CY7B9920 Low Skew Clock Buffer Block Diagram Description Features • • • • • • • • • Phase Frequency Detector and Filter All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • • • • • • • • • Block Diagram Description All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs Outputs drive 50Ω terminated lines

Contextual Info: fax id: 3516 CY7B9910 CY7B9920 •■mmmmggf ¿mw Low Skew Clock Buffer Block Diagram Description Features • • • • • • • • • Phase Frequency Detector and Filter All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows

Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows

Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Low Skew Clock Buffer Features Block Diagram Description • All outputs skew < 100 ps typical 250 max Phase Frequency Detector and Filter ■ 15 to 80 MHz output operation ■ Zero input to output delay ■ 50% duty cycle outputs

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 W ances as low as 50 while delivering miniĆ mal and specified output skews and fullĆ swing logic levels CY7B9910 TTL or CY7B9920 CMOS . Features D All outputs skew <100 ps typical (250 max.) D D D D D D D 15Ć to 80ĆMHz output operation

CY7B9910

Abstract: CY7B9920 BUT12
Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Low Skew Clock Buffer Features Block Diagram Description • All outputs skew < 100 ps typical 250 max Phase Frequency Detector and Filter ■ 15 to 80 MHz output operation ■ Zero input to output delay ■ 50% duty cycle outputs

Contextual Info: fax id: 3516 CY7B9910 CY7B9920 Low Skew Clock Buffer Block Diagram Description Featu res Phase Frequency Detector and Filter • All outputs skew <100 ps typical 250 max. • 1 5 -to 80-MHz output operation These two blocks accept inputs from the reference frequency

Contextual Info: CY7B9910 CY7B9920 PRELIMINARY Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features Block Diagram Description • All Outputs Skew <100 ps typical 250 max. Phase Frequency Detector and Filter ■ 15 to 80 MHz Output Operation ■ Zero Input to Output Delay ■ 50% Duty Cycle Outputs ■ Outputs drive 50Ω terminated lines

Clock Buffers

Abstract: FCT Fast CMOS TTL Logic CY7B9910 CY7B9920
Contextual Info: PRESS RELEASE CYPRESS INTRODUCES LOW-COST, LOW-SKEW CLOCK BUFFERS "RoboClock Jr." Devices Offer Near Zero Propagation Delay, 250 ps Pin-to-Pin Skew SAN JOSE, Calif., February 20, 1995 - Cypress Semiconductor Corporation today introduced the low-cost, low-skew CY7B9910 and CY7B9920 clock buffers. The two

CY7B991-LMB

Abstract: CY7B9910 CY7B9920 EME-6300H CY7C9910
Contextual Info: Qualification Report May, 1995 QTP# 95021 Version 1.0 PROGRAMMABLE SKEWCLOCK BUFFER CY7B9910-SC CY7B9920-SC Programable Skew Clock Buffer Driver TTL Programable Skew Clock Buffer Driver (CMOS) PRODUCT DESCRIPTION (for qualification) Information provided in this document is intended for generic qualification and technically describes the Cypress part supplied:

Contextual Info: CY7B9910 CY7B9920 CYPRESS Low Skew Clock Buffer Block Diagram Description Features All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Phase Frequency Detector and Filter These two blocks accept inputs from the reference frequency (REF) input and the feedback (FB) input and generate correc­

Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Low Skew Clock Buffer Features Block Diagram Description • All outputs skew < 100 ps typical 250 max Phase Frequency Detector and Filter ■ 15 to 80 MHz output operation ■ Zero input to output delay ■ 50% duty cycle outputs

Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features Block Diagram Description • All Outputs Skew <100 ps typical 250 max. Phase Frequency Detector and Filter ■ 15 to 80 MHz Output Operation ■ Zero Input to Output Delay ■ 50% Duty Cycle Outputs ■ Outputs drive 50Ω terminated lines

CY7B9910

Abstract: CY7B9920
Contextual Info: fax id: 3516 1CY 7B9 92 0 CY7B9910 CY7B9920 Low Skew Clock Buffer Features • • • • • • • • • Block Diagram Description All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs

Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • • • • • • • • • Block Diagram Description All outputs skew <100 ps typical 250 max. 1 5 -to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs O utputs drive 50& term inated lines

Contextual Info: CY7B9910 CY7B9920 PRELIMINARY CYPRESS Low Skew Clock Buffer Features • All outputs skew <250 ps typical 500 max. • 15- to 80-MHz output operation • Zero input to output delay • 50% duty-cycle outputs • Outputs drive 50Q terminated lines • Low operating current

CY7B9910

Abstract: CY7B9920
Contextual Info: fax id: 3516 ’*“ ££¡388^ CY7B9910 CY7B9920 CYPRESS Low Skew Clock Buffer Block Diagram Description Features • • • • • • • • • Phase Frequency Detector and Filter All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation

Contextual Info: IDT59920A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT59920A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. FEATURES: • • • • • • DESCRIPTION: Eight zero delay outputs Selectable positive or negative edge synchronization

CY7B991

Abstract: CY7B9910 CY7B9911 CY7B992 CY7B9920
Contextual Info: fax id: 3613 Using CY7B991 RoboClock , CY7B9911 (RoboClock+) and CY7B9910 (Robo Jr.) in 3.3-Volt Environments Introduction The RoboClock family of low skew clock buffers includes five products listed in Table 1. Table 1. RoboClock Family Cypress Part No.

PLD 22V10

Abstract: Time Clock phase latter CY7B991 CY7B9910 CY7B9911 CYB992 SIGNAL PATH DESIGNER
Contextual Info: fax id: 3609 Innovative Designs with CY7B991/2 RoboClock , CY7B9911 (RoboClock+) and CY7B9910/20 (Robo Jr.) Clock Buffers Overview This article discusses various applications of the Cypress Phase Locked Loop-based, skew-defeating clock buffers known as RoboClock. It is assumed that the reader has a

AN1144

Abstract: AN-1144 CY7B991 CY7B9910 CY7B9911 CY7B991V CYBUS3384 Signal Path Designer
Contextual Info: Innovative Designs Using the RoboClock Family AN1144 Author: Kelly Mass Associated Project: No Associated Application Notes: None Application Note Abstract AN1144 discusses various applications of the Cypress PLL-based, skew-defeating clock buffers known as RoboClock®. It is