CY7C1338 Search Results

80486 microprocessor block diagram and pin diagram

Abstract: CY7C1338B
Contextual Info: 338B CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 32 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wraparound counter supporting either interleaved or linear burst sequence

2930D

Contextual Info: fax id: 1108 CY7C1338 :/ C Y P R E S S 128K X 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • S u p p o rts 117-MHz m ic ro p ro c e s s o r cache s y s te m s w ith zero w a it states • 128K by 32 co m m o n I/O • Low S ta n d b y Pow er 1.65 mW, L v e rs io n

CY7C1338B

Abstract: 80486 microprocessor block diagram and pin diagrams
Contextual Info: 338B CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 32 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wraparound counter supporting either interleaved or linear burst sequence

CY7C1338G

Contextual Info: CY7C1338G 4-Mbit 128K x 32 Flow-Through Sync SRAM Functional Description[1] Features • 128K x 32 common I/O • 3.3V core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) • Provide high-performance 2-1-1-1 access rate

7C1338

Contextual Info: CY7C1338G 4-Mbit 128 K x 32 Flow-through Sync SRAM 4-Mbit (128 K × 32) Flow-through Sync SRAM Features 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated

CY7C1338F-117AC

Abstract: CY7C1338F CY7C1338F-133AC CY7C1338F-133AI CY7C1338F-133BGC CY7C1338F-133BGI CY7C1345F
Contextual Info: CY7C1338F 4-Mb 128K x 32 Flow-Through Sync SRAM Features • • • • • • • • • • • 128K X 32 common I/O 3.3V –5% and +10% core power supply (VDD) 2.5V or 3.3V I/O supply (VDDQ) Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version)

80486 microprocessor block diagram and pin diagram

Abstract: CY7C1338B
Contextual Info: CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 32 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wraparound counter supporting either interleaved or linear burst sequence

Contextual Info: CY7C1338G 4-Mbit 128 K x 32 Flow-Through Sync SRAM 4-Mbit (128 K × 32) Flow-Through Sync SRAM Features 8.0 ns (100-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated

Contextual Info: CY7C1338G PRELIMINARY 4-Mbit 128K x 32 Flow-Through Sync SRAM Functional Description[1] Features • • • • • • • • • • • 128K X 32 common I/O 3.3V –5% and +10% core power supply (VDD) 2.5V or 3.3V I/O supply (VDDQ) Fast clock-to-output times

Contextual Info: CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 32 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wraparound counter supporting either interleaved or linear burst sequence

Contextual Info: PRELIMINARY CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 32 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version

Contextual Info: PRELIMINARY CY7C1338F 128K x 32 Flow-Through Sync SRAM Features Functional Description The CY7C1338F is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock

CY7C1338G

Abstract: CY7C1338G-100AXC
Contextual Info: CY7C1338G 4-Mbit 128 K x 32 Flow-through Sync SRAM 4-Mbit (128 K × 32) Flow-through Sync SRAM Features Functional Description[1] • 128 K × 32 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O supply (VDDQ) ■ Fast clock-to-output times

CY7C1338F

Abstract: CY7C1338F-117AC CY7C1338F-133AC CY7C1338F-133AI CY7C1338F-133BGC CY7C1338F-133BGI CY7C1345F
Contextual Info: CY7C1338F 4-Mb 128K x 32 Flow-Through Sync SRAM Features • • • • • • • • • • • 128K X 32 common I/O 3.3V –5% and +10% core power supply (VDD) 2.5V or 3.3V I/O supply (VDDQ) Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version)

Contextual Info: CY7C1338G 4-Mbit 128 K x 32 Flow-Through Sync SRAM 4-Mbit (128 K × 32) Flow-Through Sync SRAM Features 8.0 ns (100-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated

CY7C1338-100AC

Abstract: 80486 microprocessor block diagram and pin diagram CY7C1338 tas 5352 7c1338-100
Contextual Info: CY7C1338 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 32 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wraparound counter supporting either interleaved or linear burst sequence

80486 microprocessor block diagram and pin diagram

Abstract: CY7C1338
Contextual Info: fax id: 1108 PRELIMINARY CY7C1338 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 32 common I/O • Low Standby Power 1.65 mW, L version

CEI 23-16

Abstract: 80486 microprocessor block diagram and pin diagram CY7C1338
Contextual Info: V CYPRESS CY7C1338 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • S u p p o rts 117 -M H z m icro p ro c ess o r c a ch e s y ste m s w ith zero w ait states • 128K by 32 co m m o n I/O • Fast c io c k -to -o u tp u t tim es

cy7c1338g-100axc

Contextual Info: CY7C1338G 4-Mbit 128K x 32 Flow-Through Sync SRAM Functional Description[1] Features • 128K x 32 common I/O • 3.3V core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 8.0 ns (100-MHz version)

Contextual Info: 338B CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 32 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wraparound counter supporting either interleaved or linear burst sequence

Contextual Info: CY7C1338G 4-Mbit 128 K x 32 Flow-Through Sync SRAM 4-Mbit (128 K × 32) Flow-Through Sync SRAM Features 8.0 ns (100-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated

CY7C1338

Abstract: tas 5352
Contextual Info: CY7C1338 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 32 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wraparound counter supporting either interleaved or linear burst sequence

CY7C1338G

Contextual Info: CY7C1338G 4-Mbit 128K x 32 Flow-Through Sync SRAM Functional Description[1] Features • 128K x 32 common I/O • 3.3V core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) • Provide high-performance 2-1-1-1 access rate

CY7C1338G

Contextual Info: CY7C1338G 4-Mbit 128K x 32 Flow-Through Sync SRAM Functional Description[1] Features • 128K x 32 common I/O • 3.3V core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) • Provide high-performance 2-1-1-1 access rate