CY7C1429KV18 Search Results

CY7C1429KV18 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: CY7C1422KV18, CY7C1429KV18 CY7C1423KV18, CY7C1424KV18 36-Mbit DDR II SIO SRAM 2-Word Burst Architecture 36-Mbit DDR II SIO SRAM 2-Word Burst Architecture Features Functional Description • 36 Mbit density 4 M x 8, 4 M × 9, 2 M × 18, 1 M × 36 ■ 333 MHz clock for high bandwidth	Original	CY7C1422KV18, CY7C1429KV18 CY7C1423KV18, CY7C1424KV18 36-Mbit CY7C1429KV18, CY7C1424KV18	PDF
Contextual Info: CY7C1422KV18, CY7C1429KV18 CY7C1423KV18, CY7C1424KV18 36-Mbit DDR II SIO SRAM 2-Word Burst Architecture 36-Mbit DDR II SIO SRAM 2-Word Burst Architecture Features Configurations • 36 Mbit density 4 M x 8, 4 M × 9, 2 M × 18, 1 M × 36 CY7C1422KV18 – 4 M × 8	Original	CY7C1422KV18, CY7C1429KV18 CY7C1423KV18, CY7C1424KV18 36-Mbit CY7C1422KV18 CY7C1423KV18	PDF
Contextual Info: CY7C1422KV18, CY7C1429KV18 CY7C1423KV18, CY7C1424KV18 36-Mbit DDR II SIO SRAM 2-Word Burst Architecture 36-Mbit DDR II SIO SRAM 2-Word Burst Architecture Features Configurations • 36 Mbit density 4 M x 8, 4 M × 9, 2 M × 18, 1 M × 36 CY7C1422KV18 – 4 M × 8	Original	CY7C1422KV18, CY7C1429KV18 CY7C1423KV18, CY7C1424KV18 36-Mbit CY7C1422KV18 CY7C1423KV18	PDF
Contextual Info: CY7C1423KV18/CY7C1424KV18 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 36-Mbit density 2 M x 18, 1 M × 36 CY7C1423KV18 – 2 M × 18 ■ 333 MHz clock for high bandwidth	Original	CY7C1423KV18/CY7C1424KV18 36-Mbit CY7C1423KV18 CY7C1424KV18	PDF
Contextual Info: CY7C1423KV18, CY7C1424KV18 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 36-Mbit density 2 M x 18, 1 M × 36 CY7C1423KV18 – 2 M × 18 ■ 333 MHz clock for high bandwidth	Original	CY7C1423KV18, CY7C1424KV18 36-Mbit CY7C1423KV18	PDF
Contextual Info: CY7C1423KV18, CY7C1424KV18 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 36-Mbit density 2 M x 18, 1 M × 36 CY7C1423KV18 – 2 M × 18 ■ 333 MHz clock for high bandwidth	Original	CY7C1423KV18, CY7C1424KV18 36-Mbit CY7C1423KV18	PDF
Contextual Info: CY7C1423KV18, CY7C1424KV18 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 36-Mbit density 2 M x 18, 1 M × 36 CY7C1423KV18 – 2 M × 18 ■ 333 MHz clock for high bandwidth	Original	CY7C1423KV18, CY7C1424KV18 36-Mbit CY7C1423KV18	PDF