CY7C1512KV18 Search Results

Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 兆2-Mb典t唯Q当R 唯存存唯止RAM唯2唯 • ■ J正AG唯114版.1唯 ■ 唯样PLL核 ❐ ■ 350唯M字争唯 唯2唯 ■ ■ 唯样当当R核唯 唯 唯兆00唯M字争唯 K唯 ■ ❐ 唯K 唯350 M字争

350bz

Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1510KV18 – 8M x 8 ■ 350 MHz Clock for High Bandwidth

CY7C1512KV18-250BZXI

Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture 72-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions

Contextual Info: CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR II SRAM Two-Word Burst Architecture 72-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1525KV18 – 8 M x 9

CY7C1512KV18-250BZXC

Abstract: CY7C1512KV18-250BZC CY7C1525KV18-250BZXC MO-216
Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1510KV18 – 8M x 8 ■ 333 MHz Clock for High Bandwidth

CY7C1514KV18-333BZI

Abstract: CY7C1512KV18-300BZC
Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture 72-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions

Contextual Info: CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR II SRAM Two-Word Burst Architecture 72-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1525KV18 – 8 M x 9

Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1510KV18 – 8M x 8 ■ 333 MHz Clock for High Bandwidth

CY7C1512KV18-250BZXI

Abstract: CY7C1514KV18-300BZI CY7C1525KV18-167BZC
Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1510KV18 – 8M x 8 ■ 333 MHz Clock for High Bandwidth

Contextual Info: CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR II SRAM Two-Word Burst Architecture 72-Mbit QDR® II SRAM Two-Word Burst Architecture Configurations Features Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1525KV18 – 8 M x 9

Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1510KV18 – 8M x 8 ■ 350 MHz Clock for High Bandwidth

Contextual Info: CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR II SRAM Two-Word Burst Architecture 72-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1525KV18 – 8 M x 9

Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1510KV18 – 8M x 8 ■ 333 MHz Clock for High Bandwidth

bzx 650

Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1510KV18 – 8M x 8 ■ 350 MHz clock for high bandwidth

CY25403

Abstract: CY25403SXC CY25403SXCT CY25423SXC CY25423SXCT
Contextual Info: CY25403/CY25423/CY25483 Three PLL Programmable Clock Generator with Spread Spectrum Features • Three fully integrated phase-locked loops PLLs ■ Three clock outputs with programmable drive strength ■ Input frequency range ❐ External crystal: 8 to 48 MHz

88E1111

Abstract: Marvell PHY 88E1111 Datasheet HFJ11-1G02E VSC8240 Marvell PHY 88E1111 altera Marvell PHY 88E1111 layout PC28F00AM29EWL Marvell PHY 88E1111 MDIO read write sfp 88e1111 sfp i2c Marvell PHY 88E1111 MDIO read write
Contextual Info: 100G Development Kit, Stratix IV GT Edition Reference Manual 100G Development Kit, Stratix IV GT Edition Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com MNL-01057-1.0 Subscribe 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.