CY7C1916KV18 Search Results

CY7C1916KV18 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
CY7C1320KV18 Contextual Info:  CY7C1316KV18, CY7C1916KV18 CY7C1318KV18, CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture 18-Mbit DDR II SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36 CY7C1316KV18 – 2 M × 8	Original	CY7C1316KV18, CY7C1916KV18 CY7C1318KV18, CY7C1320KV18 18-Mbit CY7C1316KV18 333-MHz CY7C1320KV18	PDF
CY7C1318KV Abstract: CY7C1320KV18 Contextual Info:  CY7C1316KV18, CY7C1916KV18 CY7C1318KV18, CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture Features Functional Description • 18-Mbit density 2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36 ■ 333-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency	Original	CY7C1316KV18, CY7C1916KV18 CY7C1318KV18, CY7C1320KV18 18-Mbit CY7C1916KV18, CY7C1320KV18 CY7C13cal CY7C1318KV	PDF
CY7C1318KV18 Abstract: CY7C1318KV18-250 CY7C1320KV18 Contextual Info: CY7C1316KV18, CY7C1916KV18 CY7C1318KV18, CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture 18-Mbit DDR II SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36 CY7C1316KV18 – 2 M × 8	Original	CY7C1316KV18, CY7C1916KV18 CY7C1318KV18, CY7C1320KV18 18-Mbit CY7C1316KV18 CY7C1916KV18 CY7C1318KV18 CY7C1318KV18 CY7C1318KV18-250 CY7C1320KV18	PDF
CY7C1320KV18 Contextual Info: CY7C1318KV18, CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture 18-Mbit DDR II SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1318KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth	Original	CY7C1318KV18, CY7C1320KV18 18-Mbit CY7C1318KV18 333-MHz CY7C1320KV18	PDF
CY7C1318KV18-250BZXC Abstract: CY7C1320KV18 Contextual Info: CY7C1318KV18, CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture 18-Mbit DDR II SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1318KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth	Original	CY7C1318KV18, CY7C1320KV18 18-Mbit CY7C1318KV18 333-MHz CY7C1318KV18-250BZXC CY7C1320KV18	PDF
CY7C1320KV18 Contextual Info: CY7C1318KV18/CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture 18-Mbit DDR II SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1318KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth CY7C1320KV18 – 512 K × 36	Original	CY7C1318KV18/CY7C1320KV18 18-Mbit CY7C1318KV18 333-MHz CY7C1320KV18 CY7C1320KV18	PDF