CY7C254 Search Results

CY7C25442KV18

Abstract: CY7C25442KV18-300BZI 78 ball fbga thermal resistance 3M Touch Systems
Contextual Info: CY7C25442KV18 72-Mbit QDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency with ODT Features • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 333 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency

7c251

Abstract: a1s smd smd code A1s smd diode code A1s CY7C251 CY7C254 65WMB
Contextual Info: CY7C251 CY7C254 y CYPRESS 16K x 8 Power-Switched and Reprogrammable PROM • Direct replacement for bipolar PRO M s • C apable o f w ithstanding > 2001V static discharge Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed

Contextual Info: CY7C251 CY7C254 CYPRESS SEMICONDUCTOR Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 45 ns 16,384 x 8 PROM Power Switched and Reprogrammable • TTL-compatible I/O • D irect replacement for bipolar PROMs • Capable o f w ithstanding > 2001V stat­

7C251

Abstract: C2515 SMD DIODE A13 C251-5 CY7C251-45WC CY7C251 CY7C254 01d smd code smd diode code A1s 5962-895370
Contextual Info: CY7C251 CY7C254 y CYPRESS Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 45 ns • Low power — 550 mW commercial — 660 mW (military) • Super low standby power (7C251) — Less than 165 mW when deselected

CY7C2544KV18-300BZI

Contextual Info: CY7C2540KV18, CY7C2555KV18 CY7C2542KV18, CY7C2544KV18 72-Mbit QDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency with ODT Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.0 cycles:

Contextual Info: CY7C251 CY7C254 CYPRESS r — — — W SEMICONDUCTOR 16,384 x 8 PROM Power Switched and Reprogrammable • TTL-compatlble I/O • Direct replacement for bipolar PROMs • Capable of withstanding > 2001V stat­ ic discharge Features • CMOS for optimum speed/power

Contextual Info: CY7C251 CY7C254 CYPRESS SEMICONDUCTOR 16,384 x 8 PROM Power Switched and Reprogrammable Features • C M O S for optimum speed/power • Direct replacement for bipolar PRO M s • Windowed for reprogrammability • Capable o f withstanding > 2001V static discharge

Contextual Info: CY7C25442KV18 72-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports ❐ Supports concurrent transactions

Contextual Info: CY7C25422KV18 72-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • JTAG 1149.1 compatible test access port ■ Phase Locked Loop (PLL) for accurate data placement

Contextual Info: CY7C251 CY7C254 CYPRESS SEMICONDUCTOR 16,384 x 8 PROM Power Switched and Reprogrammable Features • CMOS for optimum speed/power • D irect replacem ent for bipolar PRO M s • Windowed for reprogrammability • C apable o f w ithstanding > 2001V sta tic discharge

sm 4109 smd

Contextual Info: CY7C251 CY7C254 0 CYPRESS Features • C M O S for optim um speed/power • W indowed for reprogram m ability • High speed Low power — 550 mW com m ercial — 660 mW (m ilitary) • • D irect replacem ent for b ipolar PR O M s • C apable o f w ith stan d in g > 2 0 0 1 V

C2512

Abstract: SMD DIODE A13 7C251 smd diode code a8 C2514 smd diode code A13 CY7C251 CY7C254 CY7C251-55 C25-12
Contextual Info: CY7C251 CY7C254 Features A9 1 28 VCC A8 2 27 A10 A7 3 26 A11 A6 4 25 A12 A5 5 24 A13 A4 6 23 CS1 A3 7 22 CS2 A2 8 21 CS3 A1 9 7C254 20 CS4 A0 10 19 O7 O0 11 18 O6 O1 12 17 O5 O2 13 16 O4 GND 14 15 O3 A12 512 x 256 X O5 A8 A7 A6 O4 ADDRESS DECODER A4 O3 A3

neutron

Abstract: 3M Touch Systems
Contextual Info: CY7C25442KV18 72-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports ❐ Supports concurrent transactions

CY7C251A

Contextual Info: CY7C251 CY7C254 pypp pcc 16,384 x 8 PROM Power Switched and Reprogrammable SEMICONDUCTOR Features • C M O S for optimum speed /pow er • D irect replacem ent for bipolar PRO M s • W indowed for reprogramm ability • • H igh speed — 45 ns com m ercial

Contextual Info: CY7C251 CY7C254 16K x 8 Power Switched and Reprogrammable PROM Features Functional Description • CMOS for optimum speed/power • Windowed for reprogramm ability • High speed The CY7C251 and CY7C254 are high-performance 16,384-word by 8-bit CMOS PROMs. When deselected, the

Contextual Info: CY7C251 CY7C254 CYPRESS SEMICONDUCTOR 16K x 8 PROM Power Switched and Reprogrammable Features • TTL-compatible I/O • CMOS for optimum speed/power • Direct replacement for bipolar PROMs • Windowed for reprogrammability • High speed — 45 ns Functional Description

Contextual Info: CY7C25442KV18 72-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports ❐ Supports concurrent transactions

Contextual Info: CY7C251 CY7C254 F/ CYPRESS 16K x 8 Power-Switched and Reprogrammable PROM • Direct replacement for bipolar PROMs • Capable of withstanding > 2001V static discharge Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed

CY7C2544KV18-300BZI

Abstract: CY7C2544KV18
Contextual Info: CY7C2540KV18, CY7C2555KV18 CY7C2542KV18, CY7C2544KV18 72-Mbit QDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency with ODT Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.0 cycles:

IR 2544S

Abstract: 65d smd Smd 65D AT/IR 2544S CY7C254
Contextual Info: CY7C251 CY7C254 CYPRESS SEMICONDUCTOR 16K x 8 PROM Power Switched and Reprogrammable Features • T T L -com patible I/O • CMOS for optimum speed/power • D irect rep lacem en t fo r b ip o lar PR O M s • Windowed for reprograinmability • High speed

3M Touch Systems

Contextual Info: CY7C25402KV18, CY7C25552KV18 CY7C25422KV18, CY7C25442KV18 72-Mbit QDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency with ODT Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.0 cycles:

256K x 8 SRAM CY7C128A SRAM

Abstract: 5962-86705 PLD28 5962-89935 pld20ra10 5962-89598 CY7C132 cy7c291 PLD20RA PLDC20G10
Contextual Info: Military Product Selector Guide Static RAMs Size Organization Pins DIP SMD Number Part Number Speed (ns) ICC/ISB/ICCDR (mA @ ns) 883 Availability 1K 256 x 4 22 CY7C122 5962-88594 tAA = 25, 35 90 @ 25 Now 4K 1K x 4—Separate I/O 24S CY7C150 5962-88588 tAA = 25

smd transistor w16

Abstract: transistor smd w16 PALC22V10B-15DMB 256K x 8 SRAM CY7C128A SRAM PALC22V10B-20DMB Mil JAN jm38510 Cross Reference smd cross reference smd w20 CY7C245-45WMB 455b
Contextual Info: SMD Cross Reference Listed below are the SMDs for which Cypress is an approved source of supply. Please contact your local Cypress representative or see the Cypress website www.cypress.com for the latest SMD update. All part numbers that have an X in the PPL (Preferred

SS1203

Abstract: N82S191A 27HC642 N82S191 cy7c292 cross reference cy7c291 cross reference
Contextual Info: PROM/RPROM CROSS REFERENCE AMD WSI NATIONAL WSI AM27C49 AM27C191 AM27C291 AM27PS43 AM27S43 AM27S43A AM27S45 AM27S49 AM27S51 AM27S51A AM27S191 AM27S291 WS57C49C WS57C291C WS57C291C WS57C43C WS57C43C WS57C43C WS57C45 WS57C49C WS57C51C WS57C51C WS57C191C WS57C291C