D11U Search Results

Contextual Info: Preliminary KM M375S3227BT SDRAM MODULE KMM375S3227BT SDRAM DIMM 32M x72 SDRAM DIMM with PLL & R egister based on Stacked 32M x4, 4B anks 4K Ref., 3.3V S D R AM s with SPD FEATURE G E N E R A L DESCRIPTION • Performance range The Samsung KMM375S3227BT is a 32M bit x 72 Synchro­

Contextual Info: SDRAM MODULE Preliminary KMM375S3227BT Revision History Revision 1 May 1998 - PCB type has been changed to Intel 0.6 version. - CLK Input Cap. is added by PLL Input Cap. (27pF) - CKE1 is inserted. Revision 3 (July 1998) - "REGE" description is changed. REV. 3 July 1998

CDC2510A

Abstract: KMM375S3227BT-G0 KMM375S3227BT-G8 KMM375S3227BT-GH KMM375S3227BT-GL d11u D16U
Contextual Info: Preliminary KMM375S3227BT SDRAM MODULE KMM375S3227BT SDRAM DIMM 32Mx72 SDRAM DIMM with PLL & Register based on Stacked 32Mx4, 4Banks 4K Ref., 3.3V SDRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM375S3227BT is a 32M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung KMM375S3227BT consists of eighteen CMOS Stacked

CDC2510A

Abstract: KMM377S3227BT1-GL MA2180
Contextual Info: SDRAM MODULE Preliminary KMM377S3227BT1 Revision History Revision 4 May 1998 - CLK Input Cap. is added by PLL Input Cap. (27pF) Revision 5 (July 1998) - "REGE" description is changed. REV. 5 July 1998 Preliminary KMM377S3227BT1 SDRAM MODULE KMM377S3227BT1 SDRAM DIMM (Intel 1.0 ver. Base)

D100D

Abstract: k1113 K1112 k1011 C1213A C1314A k0305 transistor c1013 k0308 K0216
Contextual Info: AND8077/D GigaCommt SiGe SPICE Modeling Kit Prepared by: Senad Lomigora and Paul Shockman http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to provide sufficient circuit schematic and SPICE parameter information to perform system level interconnect modeling for devices in

D12U

Contextual Info: M377S6428MT1 PC100 Registered DIMM Revision History Revision 0.1 April 29, 2000 - Added the description of " Staktek’s stacking technology is Samsung’s stacking technology of choice." Rev. 0.1 Apr. 2000 M377S6428MT1 PC100 Registered DIMM M377S6428MT1 SDRAM DIMM (Intel 1.0 ver. Base)

Contextual Info: SDRAM MODULE Preliminary KMM377S3227BT1 Revision History Revision 4 May 1998 - CLK input Cap. is added by PLL Input Cap. (27pF) Revision 5 (July 1998) - "REGE" description is changed. REV. 5 July 1998 Preliminary KMM377S3227BT1 SDRAM MODULE KMM377S3227BT1 SDRAM DIMM (Intel 1.0 ver. Base)

CDC2509

Abstract: MA2180
Contextual Info: SDRAM MODULE Preliminary KMM377S3227BT Revision History Revision .2 Jan. 1998 •DC Characteristics values are changed. : ICC2 N & ICC3 N •STANDARD TIMING DIAGRAM is changed . •All AC parameters are measured by module tap reference(refer to page#5) •CAS Latency is based on Reg. DIMM (In case of Unbuff. DIMM CAS Latency is 1 CLK earlier than this)

CDC2510A

Abstract: KMM375S6427T-GL KMM375S6427T-G0 KMM375S6427T-G8 KMM375S6427T-GH
Contextual Info: Preliminary KMM375S6427T SDRAM MODULE KMM375S6427T SDRAM DIMM 64Mx72 SDRAM DIMM with PLL & Register based on Stacked 64Mx4, 4Banks 4K Ref., 3.3V SDRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM375S6427T is a 64M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung KMM375S6427T consists of eighteen CMOS Stacked

Contextual Info: SDRAM MODULE Preliminary KMM375S6427T Revision History Revision 3 May 1998 - CLK Input Cap. is added by PLL Input Cap. (27pF) - CLK1 is inserted. Revision 4 (July 1998) - "REGE" description is changed. REV. 4 July 1998 ELECTRG&HCS Preliminary KMM375S6427T

Contextual Info: SDRAM MODULE Preliminary KMM377S6427T3 Revision History R e visio n 1 Feb. - 1999 Corrected CS Swapping in Block Diagram. REV. 1 Feb 1999 Preliminary KMM377S6427T3 SDRAM MODULE KMM377S6427T3 SDRAM DIMM 64M x72 SDR AM DIMM w ith PLL & R egister based on S tacked 64M x4, 4B anks, 4K Ref., 3.3V S D R A M s w ith SPD

Contextual Info: SDRAM MODULE Preliminary KMM377S6427T1 Revision History Revision 3 May 1998 - CLK input Cap. is added by PLL Input Cap. (27pF) Revision 4 (July 1998) - "REGE" description is changed. REV. 4 July 1998 Preliminary KMM377S6427T1 SDRAM MODULE KMM377S6427T1 SDRAM DIMM (Intel 1.0 ver. Base)

Contextual Info: SD R A M M O D U L E _ Prelim inary KM M 37 7S6427T1 Revision Hi story R e v is io n 3 M a y 1 9 9 8 - CLK Input Cap. is added by PLL Input Cap. (27pF) REV. 3 M a y ’98 L£CTFi£>f8SCS Prelim inary KM M 37 7S6427T1 SD R A M M O D U L E KMM377S6427T1 SDRAM DIMM (Intel 1.0 ver. Base)

CDC2510A

Abstract: KMM377S6427T1GL
Contextual Info: SDRAM MODULE Preliminary KMM377S6427T1 Revision History Revision 3 May 1998 - CLK Input Cap. is added by PLL Input Cap. (27pF) Revision 4 (July 1998) - "REGE" description is changed. REV. 4 July 1998 Preliminary KMM377S6427T1 SDRAM MODULE KMM377S6427T1 SDRAM DIMM (Intel 1.0 ver. Base)