A115-A
Abstract: C101 SN74SSTU32864D SN74SSTU32864DGKER TOP-SIDE MARKING H2 SU864D
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864D
25-BIT
SCES623A
14-Bit
A115-A
C101
SN74SSTU32864D
SN74SSTU32864DGKER
TOP-SIDE MARKING H2
SU864D
|
Untitled
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864C
25-BIT
SCES542B
14-Bit
|
Untitled
Abstract: No abstract text available
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864D
25-BIT
SCES623A
14-Bit
|
Untitled
Abstract: No abstract text available
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864D
25-BIT
SCES623A
14-Bit
|
Untitled
Abstract: No abstract text available
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864D
25-BIT
SCES623A
14-Bit
|
Untitled
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864C
25-BIT
SCES542B
14-Bit
|
Untitled
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864C
25-BIT
SCES542B
14-Bit
|
Untitled
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864C
25-BIT
SCES542B
14-Bit
|
A115-A
Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542A – JANUARY 2004 – REVISED FEBRUARY 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864C
25-BIT
SCES542A
14-Bit
A115-A
C101
SN74SSTU32864C
SN74SSTU32864CGKER
|
A115-A
Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864C
25-BIT
SCES542B
14-Bit
A115-A
C101
SN74SSTU32864C
SN74SSTU32864CGKER
|
Untitled
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864C
25-BIT
SCES542B
14-Bit
|
Untitled
Abstract: No abstract text available
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864D
25-BIT
SCES623A
14-Bit
|
Untitled
Abstract: No abstract text available
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864D
25-BIT
SCES623A
14-Bit
|
Untitled
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864C
25-BIT
SCES542B
14-Bit
|
|
A115-A
Abstract: C101 SN74SSTU32864C SN74SSTU32864CGKER
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864C
25-BIT
SCES542B
14-Bit
A115-A
C101
SN74SSTU32864C
SN74SSTU32864CGKER
|
SSTL-18
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864C
25-BIT
SCES542B
14-Bit
SSTL-18
|
S864C
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864C
25-BIT
SCES542B
14-Bit
S864C
|
A115-A
Abstract: C101 SN74SSTU32864D SN74SSTU32864DGKER SSTL-18
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864D
25-BIT
SCES623A
14-Bit
A115-A
C101
SN74SSTU32864D
SN74SSTU32864DGKER
SSTL-18
|
A115-A
Abstract: C101 SN74SSTU32864D SN74SSTU32864DGKER
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864D
25-BIT
SCES623A
14-Bit
A115-A
C101
SN74SSTU32864D
SN74SSTU32864DGKER
|
SSTL18
Abstract: No abstract text available
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864D
25-BIT
SCES623A
14-Bit
SSTL18
|
A115-A
Abstract: C101 SN74SSTU32864D SN74SSTU32864DGKER
Text: SN74SSTU32864D 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES623A – FEBRUARY 2005 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864D
25-BIT
SCES623A
14-Bit
A115-A
C101
SN74SSTU32864D
SN74SSTU32864DGKER
|
Untitled
Abstract: No abstract text available
Text: SN74SSTU32864C 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCES542B – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout
|
Original
|
PDF
|
SN74SSTU32864C
25-BIT
SCES542B
14-Bit
|
A115-A
Abstract: C101 SN74SSTU32864E SN74SSTU32864EZKER
Text: SN74SSTU32864E 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCAS802 – JULY 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2
|
Original
|
PDF
|
SN74SSTU32864E
25-BIT
SCAS802
14-Bit
A115-A
C101
SN74SSTU32864E
SN74SSTU32864EZKER
|
A115-A
Abstract: C101 SN74SSTU32864E SN74SSTU32864EZKER ddr2 DIMM PCB
Text: SN74SSTU32864E 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCAS802 – JULY 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2
|
Original
|
PDF
|
SN74SSTU32864E
25-BIT
SCAS802
14-Bit
A115-A
C101
SN74SSTU32864E
SN74SSTU32864EZKER
ddr2 DIMM PCB
|