DELTA39K165Z Search Results

DELTA39K165Z Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+	Original	Delta39Kâ 64-bit 39K200-208EQFP 39K165 39K200 -233MHz Delta39K165Z 144-FBGA	PDF
84 FBGA Abstract: 39K100 39K200 39K30 39K50 388-BGA Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs	Original	Delta39KTM 66-MHz 64-bit 39K165 208-EQFP, 484-FBGA, 388-BGA, 676-FBGA 84 FBGA 39K100 39K200 39K30 39K50 388-BGA	PDF
CY39100V484B-125BBI Abstract: programmable slew rate control IO AT17LV010-10JI CY39030V256-125MBC IO1 5V 39K100 39K165 39K30 39K50 CY39100V208B-125NTC Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+	Original	Delta39KTM 66-MHz 64-bit 39K165 MG388 CY39030 -256FBGA CY39100V484B-125BBI programmable slew rate control IO AT17LV010-10JI CY39030V256-125MBC IO1 5V 39K100 39K30 39K50 CY39100V208B-125NTC	PDF
39K100 Abstract: 39K30 39K50 Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features — Clock polarity control at each register • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2	Original	Delta39KTM 64-bit 39K200-208EQFP 39K165 39K200 -233MHz Delta39K165Z 39K100 39K30 39K50	PDF
delta39k Abstract: 39K100 39K30 39K50 Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+	Original	Delta39KTM 64-bit 39K165 MG388 CY39030 -256FBGA delta39k 39K100 39K30 39K50	PDF
bga 484 0.8mm pitch Abstract: 20532 tqfp 39K100 39K200 39K30 39K50 484FBGA CY39200V208-181NTXC CY39100V208B-125NTxC cy39030v208-125ntxc Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs	Original	Delta39KTM 66-MHz 64-bit 39K165 208-EQFP, 484-FBGA, 388-BGA, 676-FBGA bga 484 0.8mm pitch 20532 tqfp 39K100 39K200 39K30 39K50 484FBGA CY39200V208-181NTXC CY39100V208B-125NTxC cy39030v208-125ntxc	PDF