DIN13 Search Results

50-WVDC

Abstract: 50WVDC DIN11 DS90C241 DIN13 DIN23
Contextual Info: DS90C241 SER DINO DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 LVCMOS Parallel Interface < DIN8 DIN9 DIN10 DIN11 DIN12 DIN13 DIN14 DIN15 DIN16 DIN17 DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 VDDPTO VDDPT1 VDDIT VDDL VDDT DOUT+ TCLK GPO 3.3V TPWDNB = System GPO DEN = High (ON)

DIN11

Abstract: DS90UR241
Contextual Info: DS90UR241 SER DINO DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 LVCMOS Parallel Interface < DIN8 DIN9 DIN10 DIN11 DIN12 DIN13 DIN14 DIN15 DIN16 DIN17 DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 3.3V VDD VDD VDD VDD VDD VDD DOUT+ TCLK GPOs if used, or tie High (ON) | >•

IDC2X10M

Abstract: HEADER3 IDC2X BLVDS16PCB ROUT13 PWD 100 A 40 BLVDS16EVK 1287-ST 1287ST DIN11
Contextual Info: 5 4 3 2 J1 DIN0 DIN1 DIN2 DIN3 C DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IDC2X10M R1 R3 R5 R7 R9 R2 R4 R6 R8 R10 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DIN10 DIN11 DIN12 DIN13 DIN14 DIN15 TCLK B IDC2X10M

IDC2X10M

Abstract: HEADER 2 IDC2X HEADER2 DIN13 DS92LV18 1287ST 1287-ST DIN11 ROUT21
Contextual Info: 5 4 3 2 J1 DIN0 DIN1 DIN2 DIN3 C DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IDC2X10M R1 R3 R5 R7 R9 R2 R4 R6 R8 R10 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DIN11 DIN12 DIN13 DIN14 DIN15 DIN16 B DIN17 TCLK

Contextual Info: TMS320LF2407, TMS320LF2406, TMS320LF2402 DSP CONTROLLERS SPRS094E – APRIL 1999 – REVISED AUGUST 2000 D High-Performance Static CMOS Technology D D D D D External Memory Interface LF2407 – 33-ns Instruction Cycle Time (30 MHz) – 30 MIPS Performance

MAX9263

Abstract: MAX9264 prng IEC ACB symbols PJ 62 SPREAD-SPECTRUM SYSTEM
Contextual Info: 19-5644; Rev 1; 3/11 TION KIT EVALUA BLE IL AVA A HDCP Gigabit Multimedia Serial Link Serializer/Deserializer The MAX9263/MAX9264 chipset extends Maxim’s gigabit multimedia serial link GMSL technology to include highbandwidth digital content protection (HDCP) encryption

6206a

Abstract: K-Line transceiver w1p 84 st10f2xx sigma asc 333 24 pin K-line ST10F276E W1P 59 st10 Bootstrap st10273e
Contextual Info: ST10F276E 16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM Datasheet − production data Features • ■ ■ ■ ■ ■ Highly performance 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit

RXB11

Abstract: SPRU282 TMS320C5xt 0741a 68-PL
Contextual Info: TMS320F243, TMS320F241 DSP CONTROLLERS SPRS064D − DECEMBER 1997 − REVISED FEBRUARY 2006 D High-Performance Static CMOS Technology D Includes the TMS320C2xx Core CPU D D D D D − Object-Compatible With the TMS320C2xx − Source-Code-Compatible With TMS320C25

f2407

Abstract: TMS320LC2402A TMS320LC2403A TMS320LC2404A TMS320LC2406A TMS320LF2402A TMS320LF2403A TMS320LF2406A TMS320LF2407A TMS320LF2407A CPU and Instruction Set
Contextual Info: TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 D High-Performance Static CMOS Technology D External Memory Interface LF2407A

7432 encoder

Abstract: C242 F241 TMS320 TMS320C242 TMS320C25 TMS320F241 TMS320F243 XDS510
Contextual Info: TMS320C242 DSP CONTROLLER SPRS063D – DECEMBER 1997 – REVISED SEPTEMBER 2000 D High-Performance Static CMOS Technology D Includes the TMS320C2xx Core CPU D D D D D D Single 10-Bit Analog-to-Digital Converter – Object-Compatible With the TMS320C2xx – Source-Code-Compatible With

Contextual Info: > 4M C C DEVICE SPECIFICATION 33 x 32 1.25 G B IT/S D IFF E R E N T IA L CR O SSPO IN T SW ITCH S2028 GENERAL DESCRIPTION FEATURES 33 x 32 differential crosspoint switch Full broadcast switching capability Differential 10K PECL data path Configurable differential output driver

MIL-A-8625C

Abstract: register file
Contextual Info: DEVICE SPECIFICATION 1 6 x 1 6 1 . 5 G B IT/S D IF F E R E N T IA L C R O SS PO IN T SW ITCH FEATURES • • • • • • • • • S 2016 GENERAL DESCRIPTION 1 6 x 1 6 differential crosspoint switch Full broadcast switching capability DifferentiaMOK PECL data path

DS90C124

Contextual Info: DS90C241 Serializer and DS90C124 Deserializer Evaluation Kit User’s Manual NSID: SERDES24-35USB Rev 1.5 National Semiconductor Corporation Date: 2/27/2008 Page 1 of 39 Table of Contents TABLE OF CONTENTS . 2

MAX9271

Abstract: I2C address translator fakra connector 173KB RGBhv to MAX9272 IN50I FAKRA CABLE
Contextual Info: 19-6385; Rev 0; 7/12 EVALUATION KIT AVAILABLE MAX9271 16-Bit GMSL Serializer with Coax or STP Cable Drive General Description Benefits and Features The MAX9271 compact serializer is designed to drive 50I coax or 100I shielded twisted-pair STP cable. The

131-6 bj 025

Contextual Info: D S 9 9 R 1 0 3 ,D S 9 9 R 1 0 4 DS99R103/DS99R104 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer Te x a s INSTRUMENTS Literature Number: SNLS241C a t i o n a l D S 9 9 R 1 0 3 /D S 9 9 R 1 04 3 -4 0M H z D C -B alanced 2 4-B it LVD S S e ria lize r and

GS1572-IBE3

Abstract: sd 4841 p GS1572 sd 4842 cea-861 352M CEA861 HD-SDI serializer 16 bit parallel GO1555 gs1572ibe3
Contextual Info: GS1572 Multi-Rate Serializer with Cable Driver and ClockCleanerTM Key Features Description • HD-SDI, SD-SDI, DVB-ASI transmitter • Integrated SMPTE 292M and 259M-C compliant cable driver • Integrated ClockCleaner • User selectable video processing features, including:

LF48410JI30

Abstract: DIN11 HSP48410 LF48410
Contextual Info: LF48410 LF48410 DEVICES INCORPORATED 1024 x 24-bit Video Histogrammer 1024 x 24-bit Video Histogrammer DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 40 MHz Data Input and Computation Rate ❑ 1024 x 24-bit Memory Array ❑ Histograms of Images up to 4K x 4K with 10-bit Pixel Resolution

7432 encoder

Abstract: TMS320LC2402A TMS320LC2403A TMS320LC2404A TMS320LC2406A TMS320LF2402A TMS320LF2403A TMS320LF2406A TMS320LF2407A
Contextual Info: DSP CONTROLLERS SPRS145J − JULY 2000 − REVISED NOVEMBER 2004 D High-Performance Static CMOS Technology D D D D D − 25-ns Instruction Cycle Time 40 MHz

D3318

Abstract: direct pm modulation circuit PDSP16350 PDSP16488A PDSP16510A COS10
Contextual Info: PDSP16350 PDSP16350 I/Q Splitter/NCO Supersedes version in December 1993 Digital Video & DSP IC Handbook, HB3923-1 The PDSP16350 provides an integrated solution to the need for very accurate, digitised, sine and cosine waveforms. Both these waveforms are produced simultaneously, with 16

MAX15500

Contextual Info: 19-4602; Rev 0; 6/09 Industrial Analog Current/ Voltage-Output Conditioners The MAX15500/MAX15501 analog output conditioners provide a programmable current up to Q24mA, or a voltage up to Q12V proportional to a control voltage signal. The control voltage is typically supplied by an external

dsp TMS320 circuit pwm ad

Abstract: TTL 7408 07011h FUNCTIONAL DIAGRAM OF 7400 TMS320x24x 7408 TTL ci 7432 ttl logic diagram of 7432 ttl 7432 7411 3 INPUT AND gate
Contextual Info: TMS320C242 DSP CONTROLLER SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999 D D D D D – Object-Compatible With the TMS320C2xx – Source-Code-Compatible With TMS320C25 – Upwardly Compatible With TMS320C5x – 50-ns Instruction Cycle Time Pin Compatible to Emulation Device

Contextual Info: MAX9275/MAX9279 3.12Gbps GMSL Serializers for Coax or STP Output Drive and Parallel Input General Description Benefits and Features The audio channel supports L-PCM I2S stereo and up to eight channels of L-PCM in TDM mode. Sample rates of 32kHz to 192kHz are supported with sample depth up to

Contextual Info: EVALUATION KIT AVAILABLE MAX9277/MAX9281 General Description The MAX9277/MAX9281 are 3.12Gbps Gigabit Multimedia Serial Link GMSL serializers with 3- or 4-data lane LVDS input (oLDI) and a CML serial output programmable for 50Ω coax or 100Ω shielded twisted pair (STP) cable drive.

COS10

Abstract: PDSP16350 PDSP16488A PDSP16510A DIN24 PDSP16256/A
Contextual Info: PDSP16350 PDSP16350 I/Q Splitter/NCO DS3711 The PDSP16350 provides an integrated solution to the need for very accurate, digitised, sine and cosine waveforms. Both these waveforms are produced simultaneously, with 16 bit amplitude accuracy, and are synthesised using a 34 bit