DQ243 Search Results

Contextual Info: • P h ilip s S e m ico n d u cto rs ., 1^53^31 DQ24301 IbT APX P rodu ct sp e cifica tio n AUER PHILIPS/DISCRETE b?E D ^ — Schottky barrier diodes FE A T U R E S — BAS70 series Q U IC K R E F E R E N C E DATA • Low leakage current SYM BOL • Low turn-on and high breakdown

AS8S512K3

Contextual Info: ADVANCED iPEM 64 Mb ASYNC SRAM AS8S2M32PEC 64Mb, 2Mx32 CMOS 3.3V, High Speed Static RAM Integrated Plastic Encapsulated Microcircuit FEATURES DESCRIPTION Integrated Real-Time Memory Array Solution No latency or refresh cycles Parallel Read/Write Interface

HIP-66

Contextual Info: FLASH AS8FLC1M32 FIGURE 1: PIN ASSIGNMENT Top View Hermetic, Multi-Chip Module (MCM) 32Mb, 1M x 32, 3.0Volt Boot Block FLASH Array Available via Applicable Specifications: • MIL-PRF-38534, Class H FEATURES • • • • • • • • • • • •

Contextual Info: SDRAM AS4SD2M32 512K x 32 x 4 Banks 64-Mb PIN ASSIGNMENT (Top View) Synchronous SDRAM 86-Pin TSOPII FEATURES • Full Military temp (-55°C to 125°C) processing available • Configuration: 512K x 32 x 4 banks • Fully synchronous; all signals registered on positive

IS61WV51232BLL-10BLI

Abstract: IS61WV51232BLL IS64WV51232BLL IS61WV51232 IS64WV51232BLL-10BA3
Contextual Info: IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS 512K x 32 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES • High-speed access times: 8, 10, 20 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater

jeida+dram+88+pin

Abstract: jeida 88 pin jeida dram 88 pin
Contextual Info: STI321000C1 -xxVx 88-PIN CARDS 1M X 32 DRAM Card FEATURES • Performance range: ^RAC ^CAC *RC STI321000C1-60Vx 60ns 15ns 110ns STI32100OC1-7OVx 70ns 18ns 130ns STI321000C1-80Vx 80ns 20ns 150ns The Simple Technology STI321000C1 is a 1M bit x 32 Dynamic RAM high density memory card. The Simple Technology

Contextual Info: STI322000D1 -xxV 72-PIN DIMMS 2M X 32 DRAM DIMM Memory Module FEATURES GENERAL DESCRIPTION • The Simple Technology STI322000D1 is a 2M bits x 32 Dynamic RAM high density memory module. The Simple Technology STI322000D1 consist of four CMOS 2M x 8 DRAMs in 28-pin

Contextual Info: CMS4A32LAx–75Ex 128M 4Mx32 Low Power SDRAM Revision 0.6 May. 2007 Rev. 0.6, May. ‘07 CMS4A32LAx–75Ex Document Title 128M(4Mx32) Low Power SDRAM Revision History Revision No. History Draft date Remark Preliminary 0.0 Initial Draft Apr.25th, 2005 0.1

MSM5432128

Contextual Info: Pr E2L0045-17-Y1 el im DESCRIPTION The MSM5432126/8 is a new generation Graphics DRAM organized in a 131,072-word ¥ 32-bit configuration. The technology used to fabricate the MSM5432126/8 is OKI's CMOS silicon gate process technology. The device operates with a single 5 V power supply.

MAS 10 RCD

Abstract: MSM54V32128 1DQ23
Contextual Info: O K I Semiconductor_ M SM 54V 32126/8_ 131,072-Word x 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM54V32126/8 is a new generation Graphic D RAM organized in 131,072-word x 32-bit configuration. The technology used to fabricate the MSM54V32126/8 is OKI's CM O S silicon gate

EZ23

Abstract: MSM5432128
Contextual Info: O K I Semiconductor MSM5432126/8_ 131,072-Word x 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM5432126/8 is a new generation Graphic DRAM organized in 131,072-word x 32-bit configuration. The technology used to fabricate the MSM5432126/8 is OKI’s CMOS silicon gate

gw 360

Contextual Info: EDI2GG432128V 4x128Kx32 Synchronous SRAM CARD EDGE DIMM FEATURES • 4x128Kx32 Synchronous The EDI2GG432128VxxD is a Synchronous SRAM, 60 position Card Edge; DIMM 120 contacts Module, organized as 4x128Kx32. The Module contains four (4) Synchronous Burst Ram Devices,

128*64

Abstract: transistor GW 93 H GW 94 H
Contextual Info: EDI2KG464128V 4 Megabyte Synchronous Card Edge DIMM Advanced 4x128Kx64, 3.3V Synchronous Flow-Through Module Features • 4x128Kx64 Synchronous • Flow-Through Architecture • Clock Controlled Registered Bank Enables E1\, E2\, E3, E4\ • Clock Controlled Registered Address

Contextual Info: TOSHIBA THMY721661 BEG-80,-10 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 16,777,216-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY721661BEG is a 16,777,216-word by 72-bit synchronous dynamic RAM module consisting of 18 TC59S6408BFT/BFTL DRAMs and an unbuffer on a printed circuit board.

Contextual Info: EDI2CG472128V 4 Megabyte Sync/Sync Burst, Dual Key DIMM Advanced 4x128Kx72, 3.3 V Sync/Sync Burst Flow-Through 4x128K x72 Synchronous, S ynchronous Burst The E D I2C G 472128V xxD2 is a S ynchronous/S ynchro­ Flow-Through A rchitecture nous Burst SRAM , 84 position Dual Key; Double High

CYL008M162FFBU-1ABAI

Abstract: M2A2
Contextual Info: PRELIMINARY CYL008M162FFB 128-Mbit 8-Mbit x 16 Low-Power MoBL4 SDRAM Features — Deep Sleep Mode — Self Refresh Mode; standard and low power • Functionality • Temperature: –40°C to +85°C — Internal 4 Bank Operation • 8 mm x 8 mm x 1.0 mm 54-ball 0.8 mm FBGA Package

Contextual Info: ^EDI EDI2KG46464V 2 Megabyte Synchronous Card Edge DIMM ELECTRONIC DESIGNS, IN C ADVANCED 4x64Kx64, 3.3V Module Features Synchronous Flow-Through • 4x64Kx64 Synchronous • Flow-Through A rchitecture • C lock Controlled Registered Bank Enables E1\, Module, organized as 4x64Kx64. The M odule contains

Contextual Info: TOSHIBA TH MY7216E1 BEG-80 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 16,777,216-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY7216E1BEG is a 16,777,216-word by 72-bit synchronous dynamic RAM module consisting of 18 TC59S6408BFT DRAMs and an unbuffer on a printed circuit board.

Contextual Info: TO SHIBA THMY641661 BEG-80,-10 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 16,777,216-WORD BY 64-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY641661BEG is a 16,777,216-word by 64-bit synchronous dynamic RAM module consisting of 16 TC59S6408BFT/BFTL DRAMs on a printed circuit board.

W3J512M32G

Abstract: M41K256M32
Contextual Info: W3J512M32G-XBX W3J512M32G T -XB2X W3J512M36/40G(T)-XB3X *PRELIMINARY 2GB – 512M x 32/36/40 DDR3 SDRAM 1.5V – 136/204 PBGA Multi-Chip Package FEATURES BENEFITS  DDR3 Data Rate = 800, 1,066, 1333 Mb/s  74% Space savings vs. FBGA  Packages:

Contextual Info: W3J512M64K-XPBX W3J512M64K-XLBX *ADVANCED 4GB – 512M x 64 DDR3 SDRAM 1.35V – 543 PBGA Multi-Chip Package FEATURES  Address/control terminations included  DDR3 Data Rate = 800, 1,066, 1333, 1600* Mb/s  Differential clock terminations included

Contextual Info: WED9LC6816V 256Kx32 SSRAM/4Mx32 SDRAM – External Memory Solution for Texas Instruments TMS320C6000 DSP FEATURES DESCRIPTION  Clock speeds: The WED9LC6816V is a 3.3V, 256K x 32 Synchronous Pipeline SRAM and a 4Mx32 Synchronous DRAM array constructed with

M41K256M32

Contextual Info: W3J512M32K-XBX W3J512M36K T -XB2X W3J512M36/40K(T)-XB3X *PRELIMINARY 2GB – 512M x 32/36/40 DDR3 SDRAM 1.35V – 136/204 PBGA Multi-Chip Package FEATURES BENEFITS  DDR3 Data Rate = 800, 1,066, 1333 Mb/s  74% Space savings vs. FBGA  Packages:

Contextual Info: W764M32V-XSBX Not Recommended for New Designs — Replaced by W764M32V1-XBX 64Mx32 NOR Flash Multi-Chip Package 3.0V Page Mode Flash Memory  Hardware features FEATURES  Single power supply operation • Advanced Sector Protection • WP#/ACC input accelerates programming time when