DQ67L Search Results
DQ67L Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
| BE5L
Abstract: CYD18S18V18 CYD09S36V18 CYD18S36V18 SKR 175 FullFlex36 
 | Original | ||
| FullFlex36Contextual Info: PRELIMINARY FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port | Original | 36-Gb/s 484-ball 256-ball FullFlex72 CYDD36S72V18) CYDD18S72V18 XS36V18 CYDXXS18V18 BW256 FullFlex36 | |
| FullFlex36Contextual Info: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR | Original | CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 18-Mbit, 36-Mbit FullFlex72 72-bit FullFlex36 | |
| Contextual Info: CYD04S72V CYD09S72V CYD18S72V FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM Functional Description Features • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation ■ Family of 4 Mbit, 9 Mbit, and 18 Mbit devices | Original | CYD04S72V CYD09S72V CYD18S72V FLEx72â 64K/128K/256K 18-micron | |
| BE5L
Abstract: CYD04S72V CYD09S72V CYD18S72V DQ60L 
 | Original | CYD04S72V CYD09S72V CYD18S72V FLEx72TM K/128 K/256 18-micron BE5L CYD04S72V CYD09S72V CYD18S72V DQ60L | |
| be5lContextual Info: CYD04S72V CYD09S72V CYD18S72AV FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location The FLEx72 family includes 4-Mbit, 9-Mbit and 18-Mbit | Original | CYD04S72V CYD09S72V CYD18S72AV FLEx72TM 64K/128K/256K 18-Mbit 18-micron 484-ball FLEx72-E CYD18S72AV be5l | |
| FullFlex36Contextual Info: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR | Original | CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 18-Mbit, 36-Mbit FullFlex72 72-bit FullFlex36 | |
| FullFlex36
Abstract: CYDXXS36V18 400 OHM RESISTOR DQ67 
 | Original | CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 18-Mbit, 36-Mbit FullFlex72 72-bit FullFlex36 400 OHM RESISTOR DQ67 | |
| DQ12-DQ15
Abstract: CYDXXS36V18 16-SD FullFlex36 
 | Original | 18-Mbit, 36-Mbit CYDXXS36V18 CYDXXS18V18 256-Ball BW256 FullFlex36 484-ball FullFlex18 DQ12-DQ15 16-SD | |
| be5l
Abstract: CYD18S72V-133BBI CYD04S72V CYD09S72V CYD18S72V 
 | Original | CYD04S72V CYD09S72V CYD18S72V FLEx72TM 64K/128K/256K FLEx72 18-Mbit 18-Mbit CYD09S72V CYDxxS72AV be5l CYD18S72V-133BBI CYD04S72V CYD18S72V | |
| FullFlex36Contextual Info: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR | Original | CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 72-bit 484-ball 256-ball FullFlex36 | |
| CYD18S72V-133BBI
Abstract: CYD04S72V CYD09S72V CYD18S72V BE6R DQ49L 
 | Original | CYD04S72V CYD09S72V CYD18S72V FLEx72TM 64K/128K/256K FLEx72 18-Mbit 18-Mbit CYD09S72V CYDxxS72AV CYD18S72V-133BBI CYD04S72V CYD18S72V BE6R DQ49L | |
| 0c002
Abstract: BE5L CYD18S72V-100BBC BE4L 
 | Original | FLEx72TM 18-Mb FLEx72TM CYD18S72V) 18-Mb 133-MHz 484-ball BB484 FLEx72-E 0c002 BE5L CYD18S72V-100BBC BE4L | |
| BE5L
Abstract: 0C002 
 | Original | CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V18-Mb CYD18S72V FLEx72TM 18-Mb FLEx72TM BE5L 0C002 | |
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| FullFlex36
Abstract: DQ67L CYD18S72V18 
 | Original | 18-Mbit, 36-Mbit FullFlex72 72-bit FullFlex36 DQ67L CYD18S72V18 | |
| Contextual Info: CYD09S72V CYD18S72V FLEx72 3.3 V 128 K/256 K x 72 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation ■ Family of 9-Mbit, and 18-Mbit devices | Original | CYD09S72V CYD18S72V FLEx72â K/256 18-Mbit 18-micron | |
| FullFlex36
Abstract: CYD04S36V18 CYD09S36V18 CYD18S18V18 CYD18S36V18 
 | Original | 72-bit 484-ball 256-ball FullFlex72 36-Mbit: CYD36S72V18) 18-Mbit: CYD18ation FullFlex36 CYD04S36V18 CYD09S36V18 CYD18S18V18 CYD18S36V18 | |
| FullFlex36Contextual Info: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR | Original | CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 72-bit 18-Mbit, 36-Mbit FullFlex36 | |
| CYD18S18V18-200BBAXI
Abstract: FullFlex36 CYD36S18V18-167BGXI 
 | Original | FullFlex72 72-bit CYD18S18V18-200BBAXI FullFlex36 CYD36S18V18-167BGXI | |
| Contextual Info: CYD04S72V CYD09S72V CYD18S72V FLEx72 3.3 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM Functional Description Features • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation | Original | CYD04S72V CYD09S72V CYD18S72V FLEx72TM K/128 K/256 FLEx72 | |
| be5l
Abstract: CYD04S72V CYD09S72V CYD18S72V 
 | Original | CYD04S72V CYD09S72V CYD18S72V FLEx72TM K/128 K/256 FLEx72 be5l CYD04S72V CYD09S72V CYD18S72V | |
| FullFlex36
Abstract: CYD09S36V18 CYD18S18V18 CYD18S36V18 
 | Original | 72-bit 18-Mbit, 36-Mbit FullFlex36 CYD09S36V18 CYD18S18V18 CYD18S36V18 | |
| Contextual Info: CYD04S72V CYD09S72V CYD18S72V FLEx72 3.3 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM Functional Description Features • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation | Original | CYD04S72V CYD09S72V CYD18S72V FLEx72TM K/128 K/256 FLEx72 | |
| FullFlex36Contextual Info: PRELIMINARY FullFlex72, FullFlex36, and FullFlex18 Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) | Original | FullFlex72, FullFlex36, FullFlex18 36-Gb/s 484-ball 256-ball FullFlex72 CYDD36S72V18) FLEX72-E, FLEX36-E, FullFlex36 | |