DS100871 Search Results

Contextual Info: DS90CR217/DS90CR218 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 75 MHz General Description Features The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in

DS90CR217

Abstract: DS90CR217MTD DS90CR218 DS90CR218MTD MTD48
Contextual Info: DS90CR217/DS90CR218 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 75 MHz General Description Features The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in

Contextual Info: Semiconductor DS90CR217/DS90CR218 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 75 MHz Features • 20 to 75 MHz sh ift clock support This chipset is an ideal m eans to solve EMI and cable size problem s associated with w ide, high speed T T L interfaces.

DS90CR217

Abstract: DS90CR217MTD DS90CR218 DS90CR218MTD MTD48 national 644 OF595
Contextual Info: DS90CR217/DS90CR218 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link-85 MHz General Description Features The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in

DS90CR217

Abstract: DS90CR217MTD DS90CR218 DS90CR218MTD MTD48 AN1035 AN-1035
Contextual Info: DS90CR217/DS90CR218 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 75 MHz General Description Features The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in

DS90CR217

Abstract: DS90CR217MTD DS90CR218 DS90CR218MTD MTD48 Link-75
Contextual Info: DS90CR217/DS90CR218 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 75 MHz General Description Features The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in

DS90CR217

Abstract: DS90CR217MTD DS90CR218 DS90CR218MTD MTD48 signal path designer
Contextual Info: DS90CR218 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link Receiver - 75 MHz General Description Features The DS90CR217 see DS90CR217/218A datasheet transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phaselocked transmit clock is transmitted in parallel with the data