DS150PP2 Search Results

CS8900

Abstract: CS66 10BASET
Contextual Info: 4/22/97 Performance Summary: CS8900 Datasheet Change Highly-Integrated ISA Ethernet Controller DS150PP2 DEC ’95 Corrections to the CS8900 Data Sheet Page Correction 7 Figure 1.3. Typical Connection Diagram: pin labeled “HWSLEEP” should be labeled with a pin number

CS8900

Abstract: IOR 235
Contextual Info: CS8900 10.0 SWITCHING CHARACTERISTICS 16-BIT VO READ, IOCHRDY NOT USED Parameter Symbol Address, AEN, SBHE active to IOCS16 low t|OR1 Address, AEN, SBHE active to IOR active t|OR2 IOR low to SD valid tlOR3 Min Max 35 20 tlOR4 15 IOR inactive to active t|OR5

CS8900

Abstract: CS8900CQ
Contextual Info: CS8900 A Cirrus Logic Company Highly-Integrated ISA Ethernet Controller Features Description • The CS8900 is a low-cost Ethernet LAN Controller op­ timized for Industry Standard Architecture ISA Per­ sonal Computers. Its highly-integrated design elimi­

LN427

Abstract: laf 0001 power 9410b ic laf 0001 10BASE2 10BASE5 CRD8900-1 CS8900 CS8900-CQ testing motherboards using multi meter
Contextual Info: CS8900 A Cirrus Logic Company Highly-Integrated ISA Ethernet Controller Features Description • The CS8900 is a low-cost Ethernet LAN Controller op­ timized for Industry Standard Architecture ISA Per­ sonal Computers. Its highly-integrated design elimi­

CS8900

Abstract: DB15 wiring
Contextual Info: CS8900 12.0 AUI Wiring CS8900 Tx " -< i— DB15 1:1 DO + 3 DO - 10 4 \7 1:1 Cl + Col Cl 0.01 uF, - 2 39.2 i2 - 3 : 39.2 O ' > 9 1: 1 Dl + Rx Dl - T ~ " r. 5 - ; 39 .2 . n - - - 0.01 uF '— 1 - -s c -T- : - 3 9 . 2 i 2 - r 12 6 T 13 I I T ‘ +12 V 13.0 Quartz Crystal Requirements

Contextual Info: CS8900 CONTENTS 1.0 INTRO D U CTIO N . . 1.1 General Description l.2 System A pplications l.3 Key Features and Benefits . l.4 Typical Connection Diagram . . 4 4 6 7 PIN DESCRIPTIO N . 2 .1 Pin Diagram 2.2 Pin D e s c rip tio n .

CS8900

Contextual Info: CS8900 7.0 ABSOLUTE MAXIMUM RATINGS AVSS, DVSS = 0 V, all voltages with respect to 0 V. Parameter Symbol Min Max Units d V dd -0.3 -0.3 6.0 6.0 V V ±10.0 mA Analog Input Voltage -0.3 ( a V d d +) +0.3 V Digital Input Voltage -0.3 ( d V d d +) +0.3 V -55

laf 0001 power

Abstract: ic laf 0001 CS8900 laf 0001 Predecessor 10BASE2 10BASE5 CRD8900-1 CS8900-CQ testing motherboards using multi meter
Contextual Info: CS8900 Highly-Integrated ISA Ethernet Controller Features Description • Single-Chip IEEE 802.3 Ethernet Controller with • • • • • • • • • • • • Direct ISA-Bus Interface Efficient PacketPageTM Architecture Operates in I/O and Memory Space, and as DMA Slave

Contextual Info: CS8900 A Cirrus Logic Company Highly-Integrated ISA Ethernet Controller Features Description • The CS8900 is a low-cost Ethernet LAN Controller op­ timized for Industry Standard Architecture ISA Per­ sonal Computers. Its highly-integrated design elimi­

Contextual Info: CS8900 3.0 F U N C T IO N A L D E SC R IP T IO N 3.1 O verview During normal operation, the CS8900 performs two basic functions: Ethernet packet transmis­ sion and reception. B efore transm ission or reception is possible, the CS8900 must be con­ figured.

S8900

Abstract: CS8900 0146h
Contextual Info: 15.0 Glossary of Terms Acronyms AUI CRC CS CSM A /CD DA EEPROM EOF FCS FDX IA IPG ISA LA LLC MAC MAU MIB RX SA SFD SNM P SOF SQE TDR TX UTP Attachment Unit Interface Cyclic Redundancy Check Carrier Sense Carrier Sense M ultiple Access with Collision Detection

Contextual Info: CS8900 5 .0 O P E R A T IO N 5.1 M a n a g in g In te r r u p ts an d S erv icin g th e In te r r u p t S ta tu s Q u eu e The Interrupt Status Queue IS Q is used by the CS8900 to communicate Event reports to the host processor. Whenever an event occurs that

Contextual Info: CS8900 1.0 INTRODUCTION 1.1 General Description and test. P ro g ram m ab le M A C fe atu res include auto m atic re-tran sm issio n on c o llisio n , and au to ­ m atic p ad d in g o f tran sm itted fram es. T h e C S 8 9 0 0 is a true sin g le-ch ip , full-d u p lex ,

SD08-SD15

Contextual Info: CS8900 6.0 Loopback Tests TEST M O DES Loopback & Collision Diagnostic Tests In te rn a l a n d e x te rn a l L o o p b a c k an d C o llisio n tests can be u sed to verify th e C S 8 9 0 0 ’s fu n c­ tionality w hen co n fig u red fo r e ith e r 10B A SE -T

CS8900

Abstract: SA0-SA11 10BASE-T
Contextual Info: CS8900 2.0 PIN DESCRIPTION 2.1 Pin Diagram I < X-> Lo o !<X•> o </> S2 CO T~ TPJ N i + Q 0 , + < / > O Ij 3 Q ( / < </) Û ( / ) ( l ) Û Q Û ( / ) Q Û ( / } Û i + > > U J X X > > X X > > 0 0 -L -i-i. >< < < < 0 C C C Q C < < P K < < O O O O O 3

Contextual Info: CS8900 14.0 PHYSICAL DIMENSIONS D1- 100 pin TQFP ttlll llll E E1 Io MILLIMETERS DIM MIN NOM A INCHES MIN MAX NOM 1.66 MAX 0.0 6 5 A1 0.00 B 0.14 0 .2 0 0.26 0.0 0 6 0.0 0 8 0.0 1 0 C 0.40 0.51 0.60 0.016 0.0 2 0 0.0 2 4 D 15.70 16.00 16.30 0.6 1 0 0 .6 3 0

CS8900

Contextual Info: CS8900 4.0 P A C K E T P A G E A R C H IT E C T U R E Bus Interface Registers 4.1 P acketP age O verview The Bus Interface registers are used to configure the C S8900’s ISA-bus interface and to map the CS8900 into the host system ’s I/O and Memory space. M ost of these registers are written only

center tap transformer

Contextual Info: 11.0 10BASE-T Wiring NOTES: 1. If a center tap transformer is used on the RXD+ and RXD- inputs, replace the pair of Rr resistors with a single 2xRr resistor. 2. The Rt and Rr resistors are +/- 1% tolerance. 3. The CS8900 supports 100, 120, and 150£2 unshielded twisted pair cables. The proper