DS31621 Search Results
DS31621 Datasheets Context Search
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Contextual Info: GE C P L E S S E Y ISEMICONDUCTORS I DS3162-1.1 Supersedes C48 Issue 2 MA808 FRAME ALIGNER WITH OPTIONAL TIME SLOT ZERO RECEIVER The MA808 Frame Aligner chip has been primarily designed for use in equipment operating at the CCITT standard of 2048 kbit/s for 30 channel PCM data signals. |
OCR Scan |
DS3162-1 MA808 MA808 | |
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Contextual Info: DSS4320T N EW PRODU CT LOW VCE SAT NPN SURFACE MOUNT TRANSISTOR Features Mechanical Data • • • • • • • Epitaxial Planar Die Construction Ideal for Medium Power Amplification and Switching Complimentary PNP Type Available (DSS5320T) Lead Free By Design/RoHS Compliant (Note 1) |
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DSS4320T DSS5320T) OT-23 J-STD-020D MIL-STD-202, DS31621 | |
DSS5320T
Abstract: J-STD-020D
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DSS4320T DSS5320T) OT-23 J-STD-020D MIL-STD-202, DS31621 DSS5320T J-STD-020D | |
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Contextual Info: DSS4320T LOW VCE SAT NPN SURFACE MOUNT TRANSISTOR NEW PRODUCT Please click here to visit our online spice models database. Features Mechanical Data • • • • • • • Epitaxial Planar Die Construction Ideal for Medium Power Amplification and Switching |
Original |
DSS4320T DSS5320T) OT-23 J-STD-020D MIL-STD-202, DS31621 621-DSS4320T-7 DSS4320T-7 |