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DS35145 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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JESD30E
Abstract: 74AUP1G00
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Original |
74AUP1G00 74AUP1G00 DS35145 JESD30E | |
Contextual Info: 74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G00 is a single 2-input positive NAND gate with a |
Original |
74AUP1G00 74AUP1G00 DS35145 | |
Contextual Info: 74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G00 is a single 2-input positive NAND gate with a |
Original |
74AUP1G00 74AUP1G00 DS35145 | |
Contextual Info: 74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed ( Top View ) for low power and extended battery life in portable applications. ( Top View ) A 1 The 74AUP1G00 is a single 2-input positive NAND gate with a |
Original |
74AUP1G00 74AUP1G00 X2-DFN0808-4 OT353 DS35145 |