DUAL PORT SRAM PLCC Search Results
DUAL PORT SRAM PLCC Result Highlights (5)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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TC7USB42MU |
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Dual SPDT USB switch, SPDT, UQFN10B, -40 to 85 degC |
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TC74HC123AF |
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CMOS Logic IC, Dual Monostable Multivibrator, SOP16 |
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TCWA1225G |
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High Power Switch / SPDT / WCSP14 |
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TA75W393FU |
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Comparator, Bipolar (393) type Dual Comparator, 2V to 36V, SOT-25 |
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TC7MP3125FT |
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Level shifter, Bidirectional, 2-Bit x 2 Dual Supply Bus Transceiver, TSSOP16B, -40 to 85 degC |
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DUAL PORT SRAM PLCC Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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Hitachi PIX-8144
Abstract: Hitachi PIX 8144 Pix-8144 PIX 8144 hitachi 8144 CY7C025-AC dual port 16 SRAM PLCC CY7C024 CY7C0241 CY7C0251
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CY7C0251 CY7C025 CY7C0241 CY7C024 CY7C145 CY7C144 CY7C139 CY7C138 CY7C133 CY7C143 Hitachi PIX-8144 Hitachi PIX 8144 Pix-8144 PIX 8144 hitachi 8144 CY7C025-AC dual port 16 SRAM PLCC CY7C024 CY7C0241 CY7C0251 | |
dual port SRAM PLCC
Abstract: CY7C133 CY7C138 CY7C139 CY7C143 CY7C144 CY7C145 CY7C016 CY7C024 CY7C0241
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CY7C0251 CY7C025 CY7C0241 CY7C024 CY7C145 CY7C144 CY7C139 CY7C138 CY7C133 CY7C143 dual port SRAM PLCC CY7C133 CY7C138 CY7C139 CY7C143 CY7C144 CY7C145 CY7C016 CY7C024 CY7C0241 | |
96182
Abstract: 9715 cy7c136
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CY7C130/131 CY7C140/141 CY7C132/136 CY7C142/146 CY7C13 /CY7C14* CY7C136 52-Lead CY7C025-JC CY7C025-AC 96182 9715 cy7c136 | |
CY7C136
Abstract: ablestik 84-1LMISR4 Nitto MP 8000
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CY7C130/131/140/141 CY7C132/136/142/146 CY7C13 /CY7C14* CY7C136 52-Lead CY7C0251-AC CY7C136 ablestik 84-1LMISR4 Nitto MP 8000 | |
Contextual Info: DUAL PORT RAMS MOSEL offers four Dual Port SRAMs in the 1K, 2K, and 4K x 8 densities. An 8K x 8 Dual Port SRAM is planned as a further extension to the product family. Dual Port SRAM provides two independent ports with separate controls, address and I/O data pins. The Dual Port SRAM can double the data bus bandwidth by permitting independent, |
OCR Scan |
600mil | |
7133 A-1
Abstract: AN-91 IDT7024 8K RAM 71421
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AN-91 7133 A-1 AN-91 IDT7024 8K RAM 71421 | |
7134
Abstract: DUAL-PORT STATIC RAM AN-91 IDT7024 low power asynchronous SRAM 64KX8 3.3V 1Kx8 static ram 71421
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AN-91 7134 DUAL-PORT STATIC RAM AN-91 IDT7024 low power asynchronous SRAM 64KX8 3.3V 1Kx8 static ram 71421 | |
70CMSContextual Info: MOSEL _ MS61342 PRELIMINARY 4K X 8 CMOS Dual Port SRAM FEATURES DESCRIPTION • High-speed-35/45/55ns The MOSEL MS61342 is a 32,768 bit dual port static random access memory organized as 4,096 words by 8 bits allowing each port to independently access any |
OCR Scan |
MS61342 High-speed-35/45/55ns 325mW MS61342 PID074 J52-1 S61342-35JC S61342-45JC 70CMS | |
Contextual Info: MS61342 FEBRUARY 1992 4K x 8 CMOS Dual Port SRAM FEATURES DESCRIPTION • The MOSEL MS61342 is a 32,768 bit dual port static random access memory organized as 4,096 words by 8 bits allowing each port to independently access any location in memory. A busy flag provides arbitration |
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MS61342 MS61342 52-pin 325mW 61342-45JC 52-Pin 61342I 61342-70JC | |
ms6132Contextual Info: MS6132 FEBRUARY 1992 2K x 8 CMOS Dual Port SRAM FEATURES DESCRIPTION • The MOSEL MS6132 is a 16,384 bit dual port static random access memory organized as 2,048 words by 8 bits allowing each port to independently access any location in memory. A busy flag provides arbitration |
OCR Scan |
MS6132 MS6132 48-pin 52-pin PID068A MS6132-45PC MS6132-55PC MS6132-70PC | |
Contextual Info: MS6134 FEBRUARY 1992 4K x 8 CMOS Dual Port SRAM FEATURES DESCRIPTION • High-speed - 45/55/70 ns • M S6134 — Standalone device • True Dual Port Memory array • Low Power dissipation The M OSEL M S6134 is a 32,768 bit dual port static random access memory organized as 4,096 words by 8 |
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MS6134 S6134 S6134 capabilit52-1) PID083A MS6134-45PC MS6134-55PC MS6134-70PC | |
CY7C1342
Abstract: CY7C135
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CY7C135 CY7C1342 65-micron 7C1342 52-pin CY7C135 CY7C1342 | |
Contextual Info: CY7C135 CY7C1342 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 4K x 8 organization • 0.65-micron CMOS for optimum speed/power |
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CY7C135 CY7C1342 65-micron 7C1342 52-pin CY7C135 CY7C1342 | |
sem 2005
Abstract: CY7C1342 CY7C135
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CY7C135 CY7C1342 65-micron 7C1342 52-pin CY7C135 CY7C1342 sem 2005 | |
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Contextual Info: LH540203 CMOS 2048 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing |
OCR Scan |
LH540203 LH540203 32-pin, 450-mil 28-pin, 300-mil DIP28-W-300) | |
32PLCCContextual Info: LH540202 CMOS 1024 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing |
OCR Scan |
LH540202 LH5497 Am/IDT/MS7202 LH5497H 28-Pin, 300-mil 300-miis0j* 32-Pin 32-pin, 32PLCC | |
Contextual Info: CY7C135, CY7C135A CY7C1342 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 4K x 8 organization ■ 0.65 micron CMOS for optimum speed and power |
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CY7C135, CY7C135A CY7C1342 CY7C135/135A CY7C1342 | |
CYPRESS CROSS REFERENCE dual port sram
Abstract: CY7C1342 CY7C135
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CY7C135 CY7C135A CY7C1342 7C1342 52-pin CY7C135/135A CY7C1342 CYPRESS CROSS REFERENCE dual port sram CY7C135 | |
CYPRESS CROSS REFERENCE dual port sram
Abstract: CY7C1342 CY7C135
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CY7C135, CY7C135A CY7C1342 CY7C135/135A CY7C1342 CYPRESS CROSS REFERENCE dual port sram CY7C135 | |
Contextual Info: LH540203 CMOS 2048 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing |
OCR Scan |
LH540203 LH540203 32PLCC PLCC32-P-R450) 32-pin, 450-mil 28-pin, | |
Contextual Info: LH540202 CMOS 1024 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing |
OCR Scan |
LH540202 LH540202 32-pin 450-mil 28-pin, 300-mil DIP28-W-300) | |
70V24
Abstract: CY7C024AV
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HDV24 HDV24L15PF 3HD166A 70V24 CY7C024AV | |
hd26 pinout
Abstract: sem 2107 A12L A13L J03A HD-26
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84-pin HD26L15J 3HD163A hd26 pinout sem 2107 A12L A13L J03A HD-26 | |
70V26
Abstract: A12L A13L free sem 2107
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HDV26 84-pin HDV26L15J 3HD163A 70V26 A12L A13L free sem 2107 |