signal path designer
Abstract: No abstract text available
Text: PRELIMINARY DEVICE SPECIFICATION Q20000 SERIES ECL/TTL TURBO" LOGIC ARRAYS 020000 FEATURES • Up to 24000 gates, channelless architecture • 100ps equivalent gate delays • Ultra low power ,5-1.0mW/gate • 10K, 10KH, 100K ECL and mixed ECL/TTL capability
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Q20000
100ps
SA/D1203-1089
signal path designer
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CTR34
Abstract: FGE2000 BL33B DFI01 Fairchild ZN 1010 L1332 JKI02 ctr-34 SHR04 OAI43
Text: NATL SEMICOND -CMEnORY> □2E D | ts D iia b □□bi3n ? I FGE Series ECL Gate Arrays FAIRCHILD A Schlumberger Company Description FGE Series Features The FGE Series of ECL gate arrays are the fastest silicon gate arrays commercially available. These advanced ECL gate ar
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F100K
225-picosecond
andRS003
TTRS103
Controller/16-out
CTR34
FGE2000
BL33B
DFI01
Fairchild ZN 1010
L1332
JKI02
ctr-34
SHR04
OAI43
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L100k
Abstract: No abstract text available
Text: Single PRELIMINARY , , Copy v “ 1 3 l l Q 1 0 DEVICE SPECIFICATION \ QM1600S ECL/TTL LOGIC ARRAY WITH RAM FEATURES ECL LOGIC AND RAM COMBINED 002335 The QM1600S is configured to provide up to 1600 equi valent gates of high speed ECL logic coupled with 1280
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QM1600S
QM1600
L100k
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am2022
Abstract: am22 full adder circuit using xor and nand gates AM2031 AM2024 AM2051 t950 half adder circuit using nor and nand gates ax253 AM290
Text: Am 3525 Mask-Programmable Gate Array With ECL RAM PRELIMINARY > 3 DISTINCTIVE CHARACTERISTICS Up to 3718 equivalent gates - 416 internal cells - Up to 135 l/O s 1152 bits of ECL RAM 1K with byte-wide parity - Worst case T a a (access time) = 5.5 ns High-performance, low-power ECL gates
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Am3525
Am3525
TC002800
WF010980
7321A
D7322A
am2022
am22
full adder circuit using xor and nand gates
AM2031
AM2024
AM2051
t950
half adder circuit using nor and nand gates
ax253
AM290
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Fairchild ZN 1010
Abstract: GENERAL INSTRUMENT west 2500 ic ZN 415 FGE2000
Text: FGE Series ECL Gate Arrays PAIRCHIL.D A Schlum berc T'HO Qr>y 005596 January 1986 Description U/v\A m b The FGE Series of ECL gate arrays are the fastest silicon gate arrays com m ercially available. These advanced ECL gate arrays, ranging from 100 to 2840 equivalent gates, offer
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F100K,
FGE2500)
28ngton
Fairchild ZN 1010
GENERAL INSTRUMENT west 2500
ic ZN 415
FGE2000
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TR20X3
Abstract: DFI01 OR02D
Text: December 1989 FGA S eries A S PE C T- ECL G ate A rrays General Description The FGA Series is a new generation of ECL gate arrays based on National’s ASPECT process. These advanced ECL gate arrays, ranging from 200 to over 30,000 equiva lent gates, offer typical internal propagation delays of
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FGE0500
Abstract: FGE2000 FGE2500 F100K ECL 300 series and design guide Fairchild 100K series ECL Fairchild ZN 1010 1240 picosecond la 4440 LA 4440 circuit diagram PS-1050
Text: FGE Series ECL Gate Arrays F A IR C H IL D A Schlumberc J/n A 005596 January 1986 n Description 0r>y ^ Gate Array Division FiC The FGE Series of ECL gate arrays are the fastest silicon gate arrays commercially available. These advanced ECL gate arrays, ranging from 100 to 2840 equivalent gates, offer
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F100K
225j3
FGE0500
FGE2000
FGE2500
F100K ECL 300 series and design guide
Fairchild 100K series ECL
Fairchild ZN 1010
1240 picosecond
la 4440
LA 4440 circuit diagram
PS-1050
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Q20P010
Abstract: Q20M100 carry look ahead adder Q20080 Q20P025 Q20025 vernier Q20000 Q20004 Q20010
Text: D EV IC E SP EC IFIC A TIO N LOGIC ARRAYS Q20000 “TURBO” ECL/TTL Q20000 FEATURES Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 10OK ECL and mixed ECL/TTL capability
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Q20000
Q20000
0Q03RL
Q20P010
Q20M100
carry look ahead adder
Q20080
Q20P025
Q20025
vernier
Q20004
Q20010
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signal path designer
Abstract: No abstract text available
Text: PRELIMINARY D E V IC E S P E C IF IC A T IO N 320000 SERIES ECL/TTL "TURBO" LOGIC ARRAYS 020000 FEATURES PERFORMANCE SUMMARY PARAMETER Typical gate delay* Maximum toggle frequency Maximum TTL input frequency Maximum TTL output frequency Maximum ECL input frequency
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/D1203-0589
signal path designer
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Q3500
Abstract: 300MHZ ECL100K ECL10K QM1600 QM1600S bcd counter using t flip flop diagram Vcc-1105
Text: Single PRELIMINARY ^ Copy .\ / •— “ * r 1 vi j I \ i U * * 1 11 ■ Z Z H / v Z Z Z z DEVICE SPECIFICATION QM1600S ECL/TTL LOGIC ARRAY WITH RAM FEATURES ECL LOGIC AND RAM COMBINED The Q M 1600S is con figu red to pro vid e up to 1600 e q u i valent ga tes of high spe ed ECL logic c o u p le d with 1280
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QM1600S
QM1600
B96tiHfiB
Q3500
300MHZ
ECL100K
ECL10K
bcd counter using t flip flop diagram
Vcc-1105
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HA 1370 schematics
Abstract: CMOS XNOR XOR NAND2 NAND3 ic ttl and not xor nor xnor or MICRON POWER RESISTOR 2W ECL IC NAND
Text: PRELIMINARY Semiconductor December 1990 NGM Series ABiC BiCMOS/ECL Gate Arrays General Description Features The NGM Series is a new family of mixed ECL and BiCMOS gale arrays based on National’s revolutionary 0.8 micron drawn ABiC BiCMOS process. The NGM Series is the first
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TL/U/10861-4
HA 1370 schematics
CMOS XNOR XOR NAND2 NAND3
ic ttl and not xor nor xnor or
MICRON POWER RESISTOR 2W
ECL IC NAND
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ECL2515
Abstract: ECL2516 ECL2500
Text: TYPES ECL2515, ECL2516 EMITTER-COUPLED-LOGIC ARITHMETIC MODULES ECL INTEGRATED CIRCUITS ra -h ECL2500 SERIES EMITTER-COUPLED-LOGIC ECL ARITHM ETIC MODULES FOR APPLICATION IN ULTRA-HIGH-SPEED D IG ITAL SYSTEMS c< r "0 i-m mw Hm i? 02 o-01 f- m description
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ECL2515,
ECL2516
ECL2500
ECL2516.
ECL2515
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AM2019
Abstract: 2-bit half adder layout AX253 AX201 AM2001 AX261
Text: * Am3525 Mask-Programmable Gate Array With ECL RAM PRELIMINARY > 3 DISTINCTIVE CHARACTERISTICS • • • Up to 3718 equivalent gates - 416 internal cells - Up to 135 l/O s 1152 bits of ECL RAM 1K with byte-wide parity - Worst case T a a (access time) = 5.5 ns
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Am3525
TC002800
7321A
7322A
AM2019
2-bit half adder layout
AX253
AX201
AM2001
AX261
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Silicon npn TRANSISTOR TCNL 100
Abstract: tcnl 100 TRANSISTOR TCNL 100 ECL IC NAND MUX4E schematic of TTL XOR Gates TSN2 tcnl transistor ic xnor XOR23
Text: T & T MELEC I C b4E D • DOSGQEb OOlGSlfc, Preliminary Data Sheet May 1992 a TG2 ■ ATT? &t M icroelectronics a t BEST-1 Series High-Performance ECL Gate Arrays Features Description ■ 1,000 and 4,000 equivalent logic gates The BEST-1 Series High-Performance ECL Gate
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005002b
001021b
Silicon npn TRANSISTOR TCNL 100
tcnl 100
TRANSISTOR TCNL 100
ECL IC NAND
MUX4E
schematic of TTL XOR Gates
TSN2
tcnl transistor
ic xnor
XOR23
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LT016
Abstract: LT08 YD-350 ecu schematics AIX200 LT08C LBd8 AIX2024 COF2001
Text: ADV faCRO PLA/PLE/ARRAYS 13E D Am353 b oas?sat, aoaasib 1 1 Mixed ECL/TTL I/O Mask-Programmable Gate Array > 3 DISTINCTIVE CHARACTERISTICS Integrated up to 410 ECL-equivalent gates in a 24-pin slim DIP , to eliminate "g lu e " logic, resulting in reduced
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Atn353
24-pin
AIS-WCP-15M-9/88-0
LT016
LT08
YD-350
ecu schematics
AIX200
LT08C
LBd8
AIX2024
COF2001
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AM2001
Abstract: AM223 full adder circuit using nor gates AM2005 AX202 AM2031 AM319 abx2002 full adder circuit using xor and nand gates ax253
Text: Am 3500 Mask-Programmable ECL G ate Array PRELIM IN ARY > 3 DISTINCTIVE CHARACTERISTICS • • Up to 4988 equivalent gates - 576 internal cells - Up to 134 l/O s H igh-perform ance, low -pow er ECL gates - W orst case Tpcj = 0.6 ns Hi-Speed = 0.7 ns (Medium)
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Am3500
Am3500
TC002800
WF010980
7321A
7322A
AM2001
AM223
full adder circuit using nor gates
AM2005
AX202
AM2031
AM319
abx2002
full adder circuit using xor and nand gates
ax253
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SH100E
Abstract: siemens SH100E elxr siemens Nand gate SH100E5 TRANSISTOR K 2191
Text: 7 1991 SIEMENS ASIC Product Description SH100E ECL/CML Gale Amy Family FEATURES • Gate complexities from 1,500 to 16,000 gates ■ 120 ps gate delay, 90 ps differential • 1.5 GHz D flip-flop, 1.7 GHz differential ■ Both ECL and CML macro families ■ TTL I/O available
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SH100E
10KH/100K
M33S001
SH100E
siemens SH100E
elxr
siemens Nand gate
SH100E5
TRANSISTOR K 2191
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ET3004M
Abstract: CS31E 4input nor gate ET-3004M
Text: FUJITSU MICROELECTRONICS 31E D • 374^7^2 D014b2b 7 ■ F M I cP February 1990 Edition 1.1 - FUJITSU D A TA S H EE T ET2004M, ET2009M, ET3004M ET-M Series Gate Arrays DESCRIPTION The Fujitsu ET-M Series of ECL Gate Arrays are designed to provide both fast ECL
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D014b2b
ET2004M,
ET2009M,
ET3004M
ET-2009M
ET-3004M
ET2004M
ET2009M
149-LEAD
ET3004M
CS31E
4input nor gate
ET-3004M
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74LS86 motorola
Abstract: 74LS86 full adder motorola 74LS86 74HG74 TTL 74ls83 74ls74 ALL 74LS74 motorola 74LS74 TTL 74ls74 MCA1200ECL
Text: LOGIC PRODUCTS — SEMICUSTOM continued Motorola Macrocell Array Families ft/i/t/t/t/t/t/à i / l / j / i / 1 / f/f /i Technology TTL ECL ECL/TTL 3-Mlcron Sllicon-Gate HCMOS 2-IMicron Sllicon-Gate HCMOS G ate E qu iva le nt 652 1192 2472 533 1280 2720 2958
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74LS83
MC10180
74HC283
74LS86 motorola
74LS86 full adder
motorola 74LS86
74HG74
TTL 74ls83
74ls74
ALL 74LS74
motorola 74LS74
TTL 74ls74
MCA1200ECL
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LH202
Abstract: LH293 motorola mca nor gate using TTL transistor I400 I403 LH201 h54 motorola mpa1
Text: Ami 850 Mixed ECL/TTL I/O Mask-Programmable Gate Array PRELIMINARY > 3 DISTINCTIVE CHARACTERISTICS Up to 1800 equivalent gates - 72 internal cells - Up to 80 l/O s H igh-perform ance, low -pow er ECL internal gates - W orst case T pd = 1.2 ns oo cn Large m acrocell library containing over 150 functions
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7429A
CA2068
7287A
LH202
LH293
motorola mca
nor gate using TTL
transistor
I400
I403
LH201
h54 motorola
mpa1
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LBD8
Abstract: lt08 LT016
Text: ADV KICRO PLA /P LE /A R R A YS 13E D 1 05S7Sat. Q O a flà lt *1 I Am3530 Mixed ECL/TTL I/O Mask-Programmable Gate Array > 3 DISTINCTIVE CHARACTERISTICS GO 01 Integrated up to 410 ECL-equivalent gates in a 24-pin slim DIP , to eliminate "g lu e " logic, resulting in reduced
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05S7Sat.
Am3530
24-pin
Alb-WCP-15M-9/88
LBD8
lt08
LT016
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carry look ahead adder
Abstract: Q20010 Q20120 Q20000
Text: DEVICE SPECIFICATION LOGIC A R R A Y S 020000 Q20000 FEATURES T U R B O ” ECL/TTL Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 100KECL and mixed ECL/TTL capability
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Q20080
Q20000
100KECL
Q20004
Q20010
Q20025
Q20045
Q20080
Q20120
carry look ahead adder
Q20120
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ECL2515
Abstract: ECL2500 ECL2516
Text: TYPES ECL2515, ECL2516 EMITTER-COUPLED-LOGIC ARITHMETIC MODULES ECL INTEGRATED CIRCUITS 09 H C -< ECL2500 SERIES E M ITT E R -C O U P LE D -LO G IC ECL A R IT H M E T IC M O D U LES FOR A P P L IC A T IO N IN U LTR A -H IG H -SPEED D IG IT A L SYSTEMS r-o
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ECL2515,
ECL2516
ECL2500
ECL2515
ECL2516.
ecl2516
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ZX03
Abstract: L328 H331 transistor transistor h331 ZX-03 H375 L322 L817 MCA10000ECL LH5022
Text: Order this data sheet by MCA10000ECL/D MOTOROLA MCA10000ECL ^ SEMICONDUCTOR TECHNICAL DATA M C A 10000E C L M ACRO CELL ARRAY M C A 3 ECL S E R IE S The MCA10000ECL A rra y is a m e m b e r o f M o to ro la 's "T h ird G e n e ra tio n " MCA3 ECL series. M o to ro la 's MOSAIC III process
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MCA10000ECL/D
MCA10000ECL
ZX03
L328
H331 transistor
transistor h331
ZX-03
H375
L322
L817
LH5022
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