EI-33 UL Search Results
EI-33 UL Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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ic 74 138 DECODER
Abstract: 74LS138P 74LS138PC
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bS01122 54S/74S138 54LS/74LS138 1-6f-24 1-of-32 54/74S 54/74LS ic 74 138 DECODER 74LS138P 74LS138PC | |
marking hm2 ITContextual Info: BS , C , 2 0 1 6 3 0 , 0 3 9 , 0 5 1 s s GEN. ST. IN T . ST. 01 10 02 11 12 03 13 U 16 s m 33 m m m wj pi ili m m m m b i m m m m m m m m ei l e i e i 34 38 06 07 39 40 42 08 43 44 OD 45 46 50 46 56 60 70 72 73 70 75 76 80 81 82 REV. 90 83 DATE D E S C R IP T IO N |
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BV EI 302 2022
Abstract: BV EI 306 3365 BV EI 303 2011 BV EI 305 2800 BV EI 304 2082 BV EI 305 2057 BV EI 304 2081 BV EI 304 2047 BV EI 302 2021 BV EI 303 34
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EI 42/14,8
Abstract: EN 60742 EI-30/18 EI 33 transformer EI 33 bobbin EI 48/16,8 EI 16 bobbin 44108 44240 EI transformer 38/13.6
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UL94V-O 4200Vrms EI 42/14,8 EN 60742 EI-30/18 EI 33 transformer EI 33 bobbin EI 48/16,8 EI 16 bobbin 44108 44240 EI transformer 38/13.6 | |
Contextual Info: 547 54F/74F547 Connection Diagrams Octal D ecoder/D em ultiplexer W ith Address Latches and A cknow ledge [T ïi] 5 4 w r [7 H ]A 2 r d [T 7 f] LE Description • • • • 0[I 15] Ë1 Ai [7 ~h| E 2 5 |T H]E3 a o ö ,[7 m G N D QÖ 3-to-8 Line Address Decoder |
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54F/74F547 54F/74F | |
74F547
Abstract: demultiplexer truth table truth table for 8 to 3 decoder F547
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54F/74F547 54F/74F 74F547 demultiplexer truth table truth table for 8 to 3 decoder F547 | |
Contextual Info: M aiey w tK : SLW a NO. PINS PER ROW D O’i B B Ul W PLATING OPTION P i ROW OPTION Specifications: SLW Same as CES Series except: Contact Material: Phosphor Bronze Insertion Depth: 2.16mm .085" to (2,92mm) . ’ '5 " Insertion Force: (3.34N) 12oi avg (0,64mm) .025" SQ pin |
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800-SAMTEC-9 10i8141 37T65-0- rO-8141 | |
EI - 33 TRANSFORMER
Abstract: VDE 0570 EI 33 TRANSFORMER EI 19 X 6.5 TRANSFORMER EI TRANSFORMER specification EI core transformer ei 14 transformer EI 54 TRANSFORMER transformer EI 33 transformer specification
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0570/EN UL506 APT30/2/18 APT30/2/24* EI - 33 TRANSFORMER VDE 0570 EI 33 TRANSFORMER EI 19 X 6.5 TRANSFORMER EI TRANSFORMER specification EI core transformer ei 14 transformer EI 54 TRANSFORMER transformer EI 33 transformer specification | |
Contextual Info: QL2007 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility R ev. E pASIC 2 HIGHLIGHTS 5 Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance |
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QL2007 -16-bit 1741/Os | |
PEH536YDF3270M2
Abstract: IEC 384-4 PEH536 PEH536PCC4100M2 BC 536 PEH 160 BD 140 transistor EI-40 EK 110 PEH536VCD3180M2
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curre10 PEH536YDF3270M2 IEC 384-4 PEH536 PEH536PCC4100M2 BC 536 PEH 160 BD 140 transistor EI-40 EK 110 PEH536VCD3180M2 | |
Rifa PEH 165
Abstract: Rifa PEH536 BC 536 rifa capacitor peh 200 capacitor electrolytic BC 116 ups system Rifa PEH 536
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PEH536PCC4100M2
Abstract: BC 536 PEH536JAD4390M2 PEH536JAE4470M2 PEH536JBC4390M2 PEH536JBD4560M2 PEH536JBE4680M2 PEH536JBF4820M2 PEH536JCC4560M2 PEH536JCD4680M2
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BC 116 capacitor
Abstract: em 179 Rifa PEH536
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EI-30
Abstract: EI - 33
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compou200 EI-30 EI - 33 | |
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PEH536VCD3180M2
Abstract: PEH536 em 179
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pin diagrams of basic gates
Abstract: 100-PIN 84-PIN PL84 QL2003 QL2003-1PF100C QL2003-1PF144C QL2003-1PL84C
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QL2003 QL2003 PF100 SQ--16 PF144 09MIN, pin diagrams of basic gates 100-PIN 84-PIN PL84 QL2003-1PF100C QL2003-1PF144C QL2003-1PL84C | |
Contextual Info: 548 54F/74F548 Connection Diagrams Octal D ecoder/D em ultiplexer W ith A cknow ledge Description The 'F548 is a 3-to-8 line address decoder with four Enable inputs. Two of the Enables are Active LOW and two are Active HIGH for maximum addressing versatility. Also provided is an Active LOW Acknowledge |
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54F/74F548 | |
Contextual Info: 548 54F/74F548 Connection Diagrams Octal Decoder/Demultiplexer With Acknowledge Description 3-to-8 Line Address D ecoder M ultiple Enables for Address Extension O pen C o llector Acknow ledge Output Active LO W Decoder O utputs 20l V çç O ld IÜ Ô 3 |T |
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54F/74F548 | |
EI-30
Abstract: EI - 33 EI -40C
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16-Jul-02 EI-30 EI - 33 EI -40C | |
EN 60742
Abstract: en 60742 1,8 EN60742 EI 33 transformer 44023 44024 44018 #44018 44031 44027
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UL94V-O 4200Vrms EN 60742 en 60742 1,8 EN60742 EI 33 transformer 44023 44024 44018 #44018 44031 44027 | |
BV EI 422 1224
Abstract: BV EI 422 1222 BV EI 202 BV EI 422 BV EI 422 1225 ei42 ei 42 ba 20 BV EI 422 1226
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Contextual Info: 7,000 Gate 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility PRELIMINARY DATA pASIC 2 HIGHLIGHTS Rev. D 5 Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance |
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QL2007 PF144 09MIN, PQ208 | |
Z8932101ZEM
Abstract: Z89323 Z8932301ZEM Z89373 Z8937301ZAC windows 8 socket am2 pins p2231 vahi
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Z8937301ZAC Z89373 Z8932101ZEM Z89373 68-pin Z89323, Z89323 Z8932301ZEM Z8937301ZAC windows 8 socket am2 pins p2231 vahi | |
EI - 33 TRANSFORMER
Abstract: EI 41 transformer EI 33 TRANSFORMER ei 14 transformer UL105 2x15 EI 54/18 IEC 61558-2-6 ei 42 enec 10
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