ER502B1 Search Results

Contextual Info: 10/9/2001 Errata: CS89712 Rev. C Reference CS89712 Data Sheet revision DS502PP2 dated FEB ‘01 1. CACHE AND SDRAM INTERACTION Problem Description If the cache is not turned on for all SDRAM bus cycles, an internal bus arbitration problem may occur. This condition will cause the executing code running out of SDRAM to abort.