EUREKA TECHNOLOGY Search Results

ES500

Abstract: 16 bit single cycle mips vhdl XIP2161 32 bit single cycle mips vhdl
Contextual Info: ES500 MIPS System Controller April 26, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Eureka Technology, Inc. Documentation User Guide Design File Formats EDIF netlist Constraints File Top430a.ucf Verification

EP510

Abstract: I960 MPC860 compactflash controller
Contextual Info: Eureka Technology EP510 CompactFlash Controller Product Summary FEATURES FUNCTIONAL DESCRIPTION • Compliant to ISA bus, CompactFlash specification and PC Card/PCMCIA standards. • Allows host bus devices to access ISA bus, CompactFlash, PC Card/PCMCIA devices.

EP201

Abstract: SPARTAN-3 XC3S400 XC3S400-4 Xilinx XC2V500
Contextual Info: EP201 PowerPC Bus Master April 15, 2003 Product Specification AllianceCORE Facts Core Specifics See Table 1. Provided with Core Eureka Technology, Inc. Documentation User guide Design File Formats EDIF netlist Constraints File Top201.ucf Verification VHDL or Verilog test bench

sdram controller

Abstract: 256Mb I960 Single Data Rate SDRAM Memory Controller ep525
Contextual Info: Eureka Technology EP525 Pipeline SDRAM Controller Product Summary FEATURES • Designed with synthesizable HDL for ASIC and PLD synthesis. • Supports both discrete SDRAM chips and PC100/133 SDRAM DIMM. • Supports register mode and non-register mode SDRAM DIMM.

system bus

Abstract: 486 system bus
Contextual Info: PCI Bus Target Megafunction Solution Brief 6 Target Applications: Communications Digital Signal Processing Family: FLEX 8000 and FLEX 10K Vendor: Eureka Technology Inc. 4962 El Camino Real #108 Los Altos, CA 94022 USA Tel. 415 960-3800 Fax (415) 960-3805

vhdl code for powerpc

Abstract: EP100 MPC8260 XCV400E-FG676
Contextual Info: EP100 PowerPC Bus Slave April 15, 2003 Product Specification AllianceCORE Facts Core Specifics See Table 1. Provided with Core Eureka Technology, Inc. Documentation User guide Design File Formats EDIF netlist Constraints File Top201.ucf Verification VHDL or Verilog test bench

sdram controller

Abstract: Single Data Rate SDRAM Memory Controller EP504 I960 PCI AHB DMA memory bandwidth
Contextual Info: Eureka Technology EP504 AHB Bus to SDRAM Controller Product Summary FEATURES • SDRAM controller interfaces directly with AHB Bus and user interface. • Built-in arbitration between two access ports. • Second access port allows memory sharing with user logic devices.

XCV50PQ240

Abstract: EP520 FPGA based dma controller using vhdl vhdl code for sdram controller vhdl code dma controller sdram verilog
Contextual Info: EP520 SDRAM Controller December 5, 2000 Product Specification AllianceCORE Facts Eureka Technology, Inc. 4962 El Camino Real, Suite 108 Los Altos, CA 94022 USA Phone: +1 650-960-3800 Fax: +1 650-960-3805 E-Mail: info@eurekatech.com URL: www.eurekatech.com

of 16450 UART

Abstract: EP600 uart 16450 timing design of UART 16550 uart timing EP600 programming 16450
Contextual Info: Eureka Technology EP600 UART Product Summary FEATURES • Functionally compatible with 16550. • Supports Character 16450 and FIFO (16550) mode operations. • Designed optimized for ASIC and PLD implementations. • Synchronous design with edge triggered flip-flops based on system clock input.

EP201

Abstract: aadr
Contextual Info: EP201 PowerPC Bus Master December 5, 2000 Product Specification AllianceCORE Facts Eureka Technology, Inc. 4962 El Camino Real, Suite 108 Los Altos, CA 94022 USA Phone: +1 650-960-3800 Fax: +1 650-960-3805 E-Mail: info@eurekatech.com URL: www.eurekatech.com

3SB19

Contextual Info: EC210 PCI Bus Master/Target Megafunction Solution Brief 19 Target Applications: Bus Interface April 1997, ver. 1 Features • Family: FLEX 10K Vendor: Eureka Technology Inc. 4962 El Camino Real #108 Los Altos, CA 94022 USA Tel. 415 960-3800 Fax (415) 960-3805

PowerPC 8260

Abstract: 108MHz EP300 LFX1200B
Contextual Info: Eureka Technology Product Summary EP300 PowerPC Bus Arbiter FEATURES • Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260. • Supports up to eight PowerPC bus masters with unlimited slave device support. • Supports two outstanding bus accesses.

pcmcia

Abstract: AGL600V5 PCMCIA ram Memory Card PCMCIA IO Card Controller AGL600V5-STD
Contextual Info: Eureka Technology Product Summary EP513 PCMCIA Card Slave FEATURES • Compliant with PC Card Standard 8.0, PCMCIA 2.1/JIEDA 4.2 • Receives transaction requests from PCMCIA bus interface. • Simple user interface optimized for on-chip bus connection. • Included PCMCIA standard register set.

XCV400E-FG676

Abstract: vhdl code for powerpc EP100 MPC8260
Contextual Info: EP100 PowerPC Bus Slave December 5, 2000 Product Specification AllianceCORE Facts Eureka Technology, Inc. 4962 El Camino Real, Suite 108 Los Altos, CA 94022 USA Phone: +1 650-960-3800 Fax: +1 650-960-3805 E-Mail: info@eurekatech.com URL: www.eurekatech.com

PCI AHB bridge

Abstract: EP454 ahb slave to memory
Contextual Info: Eureka Technology EP454 AHB-to-PCI Host Bridge Product Summary FEATURES • Fully supports PCI specification 2.1 and 2.2 protocol. • Supports AHB bus protocol. • Downstream access transfer from AHB bus to PCI bus. • Upstream access transfer from PCI bus to AHB bus.

EC300

Abstract: bus arbiter
Contextual Info: Eureka Technology EC300 PCI Bus Arbiter Product Summary FEATURES • Compliant with PCI bus specification 2.2. • Designed for ASIC and PLD implementations in various system environments. • Fully static design with edge triggered flip-flops. • Supports two to any number of bus masters.

EP201

Abstract: MPC8260
Contextual Info: Eureka Technology EP201 PowerPC Bus Master Product Summary FEATURES • Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260. • Designed for ASIC or PLD implementations in various system environments. • Fully static design with edge triggered flip-flops.

sh4 CPU

Abstract: I960 MPC8260 uart dma sdram controller bus arbiter
Contextual Info: Eureka Technology System Controller Product Summary FEATURES • Designed for ASIC and PLD implementations. • Fully static design with edge triggered flip-flops. • Different versions to support ARM, I960, PowerPC and SH2-SH4 microprocessors. • Fully integrated single chip design provide complete system level functions for

PCMCIA Adapter

Abstract: EP510 LFX1200B MPC860 FPGA PCMCIA
Contextual Info: Eureka Technology Product Summary EP510 CompactFlash/PCMCIA Host Adapter FEATURES • Compliant with PC Card Standard 8.0, PCMCIA 2.1/JIEDA 4.2 and CompactFlash 1.4 • Allows host bus devices to access CompactFlash and PC Card/PCMCIA devices. • Simple user interface optimized for on-chip bus connection.

CY39100V676-200MBC

Abstract: EC220
Contextual Info: Eureka Technology EC220 32-bit PCI Master/Target Product Summary FEATURES • Fully supports PCI specification 2.1 and 2.2 protocol. • Designed for ASIC and PLD implementations. • Fully static design with edge triggered flip-flops. • Efficient back-end interface for different types of user devices.

Contextual Info: Eureka Technology EC240 64-bit PCI Bus Master/Target Product Summary FEATURES • Fully supports PCI specification 2.1 and 2.2 protocol. • Supports both 64-bit and 32-bit bus systems. • Supports dual address cycle DAC 64-bit addressing. • Designed for ASIC and PLD implementations.

Contextual Info: Eureka Technology EP440 PCI-to-PCI Bridge Product Summary • Fully supports PCI bus specification 2.2 and PCI bridge specification 1.1. • Designed for ASIC and PLD implementations. • Fully static design with edge triggered flip-flops. • Independent asynchronous PCI clocks on primary and secondary bus.

Contextual Info: Eureka Technology EP420 64-bit PCI Host Bridge Product Summary FEATURES • Fully supports PCI specification 2.1 and 2.2 protocol. • Designed for ASIC and PLD implementations. • Supports both 64-bit and 32-bit bus systems. • Fully static design with edge triggered flip-flops.

ep433

Abstract: MPC8260 MPC860 PowerPC 7400
Contextual Info: Eureka Technology EP433/434 PowerPC-PCI Bridge Product Summary FEATURES • Fully supports PCI specification 2.1 and 2.2 protocol. • Designed for ASIC and PLD implementations. • Fully static design with edge triggered flip-flops. • Supports all PowerPC CPU with 603 bus interface and MPC860 interface.