F1016 Search Results

F10166

Abstract: F10566
Contextual Info: F10166^ F10566 5-BIT COMPARATOR F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F10166/F10566 are high-speed expandable 5-Bit Comparators for comparing the magnitude of two binary words. Two outputs are provided: A>B and A<B. A = B can be obtained by NORing the two outputs with an additional gate. A HIGH level on the

F10162

Abstract: F10562 decoder active high outputs
Contextual Info: F10162 • F10562 l-OF-8 DECODER ACTIVE HIGH OUTPUTS D E S C R IP TIO N — T h e F10162 a n d F10562 a c c e p t a 3 -b it b in a r y in p u t a n d p ro v id e s e ig h t m u tu a lly e x c lu s iv e o u tp u ts . T h e s e le c te d o u tp u t w ill be H IG H w h ile a ll o th e r

F10161

Contextual Info: F10161 • F10561 l-OF-8 DECODER ACTIVE LOW OUTPUTS DESCRIPTION — The F10161 and F10561 accept a 3-bit binary input and provides eight m utually exclusive outputs. The selected output w ill be LOW while all other outputs are HIGH. Two enable inputs force all outputs HIGH when either or both are

Contextual Info: polyfet rf devices F1016 PATENTED GOLD METALIZED General Description SILICON RF POWER MOSFET Silicon DMOS designed specifically for RF applications. Immune to forward and reverse bias secondary breakdown "Polyfet" ^ process features gold metal for greatly extended

Contextual Info: F10160 • F10560 12-BIT PARITY CHECKER/GENERATOR DESCRIPTION — The F10160 and F10560 are 12-Input Parity Generators. The output w ill be HIGH when an odd number of inputs are HIGH; typical delay is 4 ns. For applications requiring fewer than 12 inputs, unused inputs may be left open, since

Contextual Info: polyfet rf devices F1016 General Description PATENTED GOLD METALIZED SILICON GATE ENHANCEMENT MODE RF POWER VDMOS TRANSISTOR Silicon VDMOS and LDMOS transistors designed specifically for broadband RF applications. Suitable for Military Radios, Cellular and Paging Amplifier Base

F10168

Abstract: F10568
Contextual Info: F101687» F 10568^ FIOK VOLTAGE COMPENSATED ECL QUAD LATCH/GATED OUTPUTS DESCRIPTION - The F10168 and F10568 contains four D type latches with a Common Enable Ec . When Ec is HIGH, outputs will follow the D inputs. Information is latched on the negative-going edge of Ec . Each latch output is combined with a separate gate control (Gn),

3bit to 8 Multiplexer

Abstract: VCC2-16 circuit diagram of 16-1 multiplexer F10164 F10564
Contextual Info: F10164 • F10564 8-INPUT MULTIPLEXER D E S C R IP TIO N — T h e F10164 a n d F10564 a c c e p t a 3 - b it a d d re s s a n d s e le c ts 1 -o f-8 LOGIC SYMBOL in p u ts . T h e e n a b le lin e , w h e n H IG H , fo rc e s th e o u tp u t L O W . T y p ic a l a d d re s s to o u tp u t

Contextual Info: F10565* F10165 8-INPUT PRIORITY ENCODER F10K VOLTAGE COMPENSATED ECL G E N E R A L DESCRIPTION - The F10165/F10565 are 8-Input Priority Encoders with output latches. The inputs are preassigned an order of priority, with D0 having the highest priority and D7 the lowest. Outputs Q2, CLi, Qo constitute a binary code identifying the highest order input

Contextual Info: F10164 • F10564 8-INPUT MULTIPLEXER D E S C R IP T IO N — The F10164 and F10564 a cce p t a 3 -b it address and selects 1-of-8 inpu ts. The enable line, w hen H IG H , fo rc e s the o u tp u t LOW. T yp ica l address to o u tp u t delays are 4 ns. LOGIC SYMBOL

Contextual Info: F10565* F10165 8-INPUT PRIORITY ENCODER F10K VOLTAGE COMPENSATED ECL GENERAL DESCRIPTION - The F10165/F10565 are 8 -Input Priority Encoders with output latches. The inputs are preassigned an order of priority, with D0 having the highest priority and D 7 the lowest. Outputs Q2, Q 1 , Q0 constitute a binary code identifying the highest order input

l1113

Contextual Info: F 10168 • F 10568 F10K VOLTAGE COMPENSATED ECL QUAD LATCH/GATED OUTPUTS DESCRIPTION - The F10168 and F10568 contains four D type latches with a Common Enable Ec . When E c is HIGH, outputs will follow the D inputs. Information is latched on the negative-going edge of E c Each latch output is combined with a separate gate control (Gn),

Contextual Info: F10162 • F10562 l-OF-8 DECODER ACTIVE HIGH OUTPUTS D E S C R IP TIO N — T h e F10162 a n d F 10562 a c c e p t a 3 - b it b in a ry in p u t a n d p ro v id e s e ig h t m u tu a lly e x c lu s iv e o u tp u ts . T h e s e le c te d o u tp u t w ill be H IG H w h ile a ll o th e r

F10161

Contextual Info: F10161 • F10561 l-OF-8 DECODER A C T IV E LO W O U T P U T S D E SC R IP TIO N — The F10161 and F10561 a cce p t a 3 -b it b in a ry in p u t and provides e ig h t m u tu a lly e x clusive o u tp u ts . The selected o u tp u t w ill be LOW w h ile all o th e r

"Parity Checker"

Abstract: PIN DIAGRAM OF RJ50 10 pin F10160 F10560 RJ-50 RJ50
Contextual Info: F10160 • F10560 12-BIT PARITY C H EC K E R /G E N E R A TO R D E S C R IP T IO N — T h e F10160 a n d F10560 a re 1 2 - In p u t P a rity G e n e ra to rs . T h e o u tp u t w ill b e H IG H w h e n a n o d d n u m b e r o f in p u ts a re H IG H ; ty p ic a l d e la y is 4 ns. F o r

F10161

Abstract: F10561
Contextual Info: F10161 • F10561 l-OF-8 DECODER ACTIVE LOW OUTPUTS D E S C R IP TIO N — T h e F10161 a n d F10561 a c c e p t a 3 - b it b in a r y in p u t a n d p ro v id e s e ig h t m u tu a lly e x c lu s iv e o u tp u ts . T h e s e le c te d o u tp u t w ill be L O W w h ile a ll o th e r

fairchild ECL

Contextual Info: F10164 • F10564 8-INPUT MULTIPLEXER D E S C R IP T IO N — The F10164 and F10564 a c c e p t a 3 -b it address and selects 1-of-8 in p u ts. T h e e n able line, w hen H IG H , fo rc e s th e o u tp u t LOW , T yp ica l address to o u tp u t delays are 4 ns.

Contextual Info: F10162 • F10562 l-OF-8 DECODER ACTIVE HIGH OUTPUTS D E S C R IP T IO N — T h e F 1 0 1 62 a n d F 1 0 5 62 a c c e p t a 3 - b it b in a r y in p u t a n d p ro v id e s e ig h t m u tu a lly e x c lu s iv e o u tp u ts . T h e s e le c te d o u t p u t w ill b e H IG H w h ile a ll o th e r

A1B11

Abstract: ecl f10k
Contextual Info: F10166^ F10566 5-BIT COMPARATOR F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F10166/F10566 are high-speed expandable 5-Bit Comparators for comparing the magnitude of two binary words. Two outputs are provided: A>B and A<B. A = B can be obtained by NORing the two outputs with an additional gate. A HIGH level on the

F10165

Abstract: F10565
Contextual Info: F 1 5 6 5 » F 1 1 6 5 ^ 8-INPUT PRIORITY ENCODER F10K VOLTAGE COMPENSATED ECL GENERAL DESCRIPTION - The F10165/F10565 are 8-Input Priority Encoders with output latches. The inputs are preassigned an order of priority, with D0 having the highest priority and

F1016

Contextual Info: polyfet rf devices F1016 General Description PATENTED GOLD METALIZED SILICON GATE ENHANCEMENT MODE RF POWER VDMOS TRANSISTOR Silicon VDMOS and LDMOS transistors designed specifically for broadband RF applications. Suitable for Military Radios, Cellular and Paging Amplifier Base

Contextual Info: F10166 • F10566 5-BIT COMPARATOR FIOK VOLTAGE COMPENSATED ECL DESCRIPTION - The F10166/F10566 are high-speed expandable 5-Bit Comparators or comparing the magnitude of two binary words. Two outputs are provided: A>B and A<B. A= B can be obtained by NORing the two outputs with an additional gate. A HIGH level on the

Contextual Info: F 1 0 1 6 0 • F 1 0 5 6 0 12-BIT PARITY CHECKER/GENERATOR D E S C R IP TIO N — The F10160 and F10560 are 1 2 -In p u t P arity G enerators. The o u tp u t w ill be H IG H w hen an odd nu m b e r o f in p u ts are H IG H ; ty p ic a l de la y is 4 ns. For

F1016

Contextual Info: F1016 LIQUID CRYSTAL DISPLAY MODULE USER’S MANUAL