F23I Search Results

Contextual Info: J uly 1988 Revised D ecem ber 1998 SE M ¡CONDUCTOR TM 74ACT843 9-Bit Transparent Latch General Description Features T h e AC T843 bus interface latch is designed to elim inate the extra packages required to buffer existing latches and provide extra data w idth for w id e r address/data paths.

Contextual Info: A I R C H April 1991 _ _i a , Revised A ugust 1999 I L D E M IC O N D U C T G R T M 74FR9245 9-Bit Bidirectional Transceiver with 3-STATE Outputs General Description Features The 74F R 9245 contains nine non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. C urrent sinking capability is 64_mA on

ADC0844

Abstract: ADC0844CCN ADC0848 ADC0848BCN ADC0848CCN
Contextual Info: Semiconductor ADC0844/ADC0848 8-Bit |iP Compatible A/D Converters with Multiplexer Options General Description Features The A D C 0844 and A D C 0848 are C M O S 8-bit successive a p ­ proxim ation A/D converters w ith versatile analog input m ulti­ plexers. The 4-channel or 8-channel m ultiplexers can be

Cj721

Abstract: transistor j3003 J3009 j3003 J3005 JS28F256P30T85 11M24 FERRITE-220 J3007 A1818
Contextual Info: 4 3 PAGE 6 PAGE 3 System Monitor Aux System Monitor 2 PAGE 2 System Ace Upstream PAGE 2 Upstream Connector 1 PAGE 5 Single Ended Socket Clocks 2X PAGE 5 PAGE 7 Differential SMA Clocks 2X Differential SMA MGT Clocks 2X D D PAGE 12-13 Power Bus and Switches

Contextual Info: “ Revised h1 Q Q « Novem ber 1998 S E M I C O N D U C T O R TM tures GTO output control and undershoot corrector in addition to sp lit ground bus for su pe rio r perform ance. General Description The AC TQ 652 utilizes Fairchild FACT Q u iet Series™ te ch ­

Contextual Info: SEMICONDUCTOR TM 74ACT652 Transceiver/Register General Description Features The ACT652 consists of bus transceiver circuits with Dtype flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked

FERRITE-220

Abstract: transistor j3003 ff1136 J3009 j3003 HDR1X12 capacitor 100nf 16v N5 JS28F256P30T85 11n34 E28 ferrite
Contextual Info: 4 3 PAGE 6 PAGE 3 System Monitor Aux System Monitor 2 PAGE 2 System Ace Upstream PAGE 2 Upstream Connector 1 PAGE 5 Single Ended Socket Clocks 2X PAGE 5 PAGE 7 Differential SMA Clocks 2X Differential SMA MGT Clocks 2X D D PAGE 16-17 Power Bus and Switches

B902

Abstract: 74*652
Contextual Info: R e v is e d A u g u s t 1 9 9 9 S E M IC Q N D U C TQ R T M 74F651 • 74F652 Transceivers/Registers General Description Features T h e s e d e v ic e s c o n s is t o f b u s tra n s c e iv e r c irc u its w ith D- • In d e p e n d e n t re g is te rs fo r A a n d B b u s e s

DM74AS874

Abstract: DM74AS874NT DM74AS874WM M24B N24C
Contextual Info: R C H II_ D S E M IC O N D U C T O R tm DM74AS874 Dual 4-Bit D-Type Edge-Triggered Flip-Flop General Description These dual 4-bit inverting registers feature totem -pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low -im pedance loads. The

J3009

Abstract: j3003 4AC14 11K21 Y25IO hdr1x8 4ac17 hdr-1x8 11K23 4ab10
Contextual Info: 4 3 PAGE 6 PAGE 3 System Monitor Aux System Monitor 2 PAGE 2 System Ace Upstream PAGE 2 Upstream Connector 1 PAGE 5 Single Ended Socket Clocks 2X PAGE 5 Differential SMA Clocks 2X D D PAGE 12 Power Bus and Switches 5V OR 5V JACK BRICK PAGE 2 Switches User Reset

JS28F256P30

Abstract: 11K33 j3003 4AG22 5B19 c225 HDR 2x5 J3009 12W8 2ae12
Contextual Info: 4 3 PAGE 6 PAGE 3 System Monitor Aux System Monitor 2 PAGE 2 System Ace Upstream PAGE 2 Upstream Connector 1 PAGE 5 Single Ended Socket Clocks 2X PAGE 5 Differential SMA Clocks 2X D D PAGE 16 Power Bus and Switches 5V OR 5V JACK BRICK PAGE 2 Switches User Reset

F23I

Abstract: 74ACT652 74ACT652MTC 74ACT652SC 74ACT652SPC M24B MS-013 MTC24 N24C
Contextual Info: Revised O ctober 1999 S E M I C O N D U C T O R TM 74ACT652 Transceiver/Register General Description Features The AC T652 consists of bus tra n sce ive r circuits w ith Dtype flip-flops, and control circuitry arranged for m ultiplexed transm ission of data directly from th e input bus or from

Contextual Info: s e m ic o n d u c t o r Revised November 1999 74ACTQ652 Quiet Series™ Transceiver/Register General Description Features The ACTQ652 consists of bus transceiver circuits with Dtype flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from

HY5117400

Abstract: WD41 HY5117400JC cs40
Contextual Info: HY5117400 Series «H YUND AI 4M x 4-bit CMOS DRAM DESCRIPTION The HY5117400 is the new generation and fast dynamic RAM organized 4,194,304 x 4-bit. The HY5117400 utilizes Hyundai’s CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating