FIF02 Search Results

SMD W2T

Abstract: w2t smd BTS 131 SMD MBA IST DATE SHEET SN54ACT3632
Contextual Info: • fl^bi723 aiiossT ist. ■ SN54ACT3632 512x36x2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY _ _ S G B S310-SEPTEM BER 1996 * Free-Running CLKA and CLKB Can Be Asynchronous or Coincident ► Two Independent 512 x 36 Clocked FIFOs

Contextual Info: 3.3 VOLT CMOS SyncBiFlFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024x36x2 Integrated Device Technology, Inc. PRELIMINARY IDT72V3624 IDT72V3634 IDT72V3644 • M aster R eset clears d ata and configures FIFO, Partial R eset clears data but retains configuration settings

Contextual Info: | CMOS Bus-Matching SyncFlFO 256 x 36, 512 x 36,1,024 x 36 dt PRELIMINARY ¡DT723633 IDT723643 Integrated D ev ic e Techno logy, Inc. NOTE: There is an errata notice on the last page and the corrections have been incorporated into this document. FEATURES:

Contextual Info: ggSi'x jjûfey CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 IDT723622 ¡DT723642 Integrated Device Technology, Inc. Advance inform ation for the IDT723622 Final for the IDT723632 Advance inform ation for the IDT723642 FEATURES: • Free-running CLKA and CLKB m ay be asynchronous or

Contextual Info: CMOS SyncBiFlFO 256x36x2, 512x36x2, 1,024x36x2 IDT723622 IDT723632 IDT723642 Hhtegiated Devize Technology, lie . NOTE: There is an errata notice on the last page and the corrections have been incorporated into this document. FEATURES: • Free-running C LK A and CLKB may be asynchronous or

Contextual Info: In te g ra te d D e v i e T e d h n o Jo g y , lie . CMOS Triple Bus SyncFlFO1 With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 PRELIMINARY IDT723626 IDT723636 IDT723646 NOTE: There are two errata notices at the end of this data sheet. The May 20 errata describes corrections that have

Contextual Info: CMOS SyncBiFlFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2 IDT723614 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB can be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted

Contextual Info: Integrated Device Technology, Inc. CMOS Sync BiFlFO With Bus-Matching 256x36x2, 512x36x2, 1,024x36x2 PRELIMINARY IDT723624 IDT723634 IDT723644 NOTE: There is an errata notice on the last page and the corrections have not been incorporated into this document.

Contextual Info: |dy Integrated Dev ice Technology, Inc. CMOS Triple Bus SyncFlFO With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 PRELIMINARY I D T y iii ll IDT723646 FEATURES: • Memory storage capacity: IDT723626-256 x 36 x 2 IDT723636-512 x 3 6 x 2 IDT723646-10 2 4 x 3 6 x 2

Contextual Info: Integrated Device TechnoJogy, lie. PRELIMINARY IDT723624 IDT723634 IDT723644 CMOS Sync BiFlFO With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 NOTE: There is an errata notice on the last page and the corrections have not been incorporated into this document.

JDS SB switch

Abstract: CY7C43644V CY7C43664V CY7C43684V CY7C43664V/CY7C43684V
Contextual Info: CY7C43644V CY7C43664V/CY7C43684V PRELIMINARY CYPRESS 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching Features — Ic c = 60 m A , lSB= 12 m A F ully a s yn ch ro n o u s and sim u ltan eo u s read and w rite o p e ratio n p erm itted FWFT Mode, Ptease See Errata Attached

Contextual Info: PRELIMINARY CY7C43644V CY7C43664V/CY7C43684V 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching Features • 3.3V high-speed, low-power, bidirectional, first-in first-out FIFO mem ories w/ bus matching capabilities • 1 Kx36x2 (CY7C43644V)

Contextual Info: CY7C43626 CY7C43636/CY7C43646 CY7C43666/CY7C43686 . PRELIMINARY 2 5 6 / 5 1 2 / 1 K /4 K / 1 6 K x 3 6 / x 1 8 x 2 T ri B u s F I F O Fully asynchronous and sim ultaneous read and write operation permitted Mailbox bypass register for each FIFO Parallel and Serial Programmable Almost-Full and Alm ost-Em pty flags

Contextual Info: - ^ n n n > CYPHhbo CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY = 256/512/1K/4K/16K x36 x2 Bidirectional Synchronous FIFO • F ully a s yn ch ro n o u s and sim u ltan eo u s read and w rite o p e ratio n p erm itted Features • H ig h -s p e ed , low -pow er, b id irec tio n al, First-In First-O ut

Contextual Info: SN74ACT3632 51 2 x 36 x 2 C L O C K E D B I D I R E C T I O N A L F I RST - I N, F I R S T - O U T M E M O R Y S C A S 224C -JU N E 1 9 9 2 - REVISED SEPTEMBER 1995 F r e e - R u n n i n g C L K A and C L K B Can Be IRB, O R B , AEB , and AFB Flags A s y n c h r o n o u s or C o i n c i d e n t

IC51-1324-828

Abstract: IDT723622 IDT723632 IDT723642
Contextual Info: IDT723622 IDT723632 IDT723642 CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted

socket Yamaichi ic51 qfp

Abstract: AI893 0R 508 9738A
Contextual Info: IDT723622 IDT723632 IDT723642 CM OS Syn cBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 NOTE: T h e r e i s an e r r a ta n o t i c e o n th e l a s t p a g e a n d th e c o r r e c t i o n s h a v e b e e n i n c o r p o r a t e d i n t o t h i s d o c u m e n t .

CHN 044 VW

Abstract: NB18
Contextual Info: CMOS SyncBiFIFO with Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 IDT723624 IDT723634 IDT723644 • Port B bus sizing ot 36-bits long word , 18-bits (word) and 9-bits (byte) • Big- or Little-Endian tormat tor word and byte bus sizes • Master Reset clears data and contigures FIFO, Partial

72V3672

Contextual Info: 3.3 VOLT CMOS SyncBiFIFO 2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2,16,384 x 36 x 2, 32,768 x 36 x 2, 65,536 x 36 x 2 FEATURES: • Memory storage capacity: ADVANCE INFORMATION IDT72V3652 IDT72V3662 IDT72V3672 IDT72V3682 IDT72V3692 IDT72V36102 Mailbox bypass register for each FIFO

Contextual Info: 3.3 VOLT CMOS SyncBiFlFO WITH BUS-MATCHING 2 5 6 x 3 6 x 2, 512 x 3 6 x 2, 1,024 x 36 x 2_ FEATURES: • Memory storage capacity: IDT72V3624-256 x 36 x 2 IDT72V3634-512 x 36 x 2 IDT72V3644-1,024x36x2 • Clock frequencies up to 83 MHz 8ns access time

723666

Contextual Info: 3.3 VOLT CMOS TRIPLE BUS SyncFlFO WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2,16,384 x 36 x 2, 32,768 x 36 x 2, 65,536 x 36 x 2 FEATURES: ADVANCE INFORMATION IDT72V3656 IDT72V3666 IDT72V3676 IDT72V3686 IDT72V3696 IDT72V36106 Serial or parallel programming of partial flags

IDT723624

Abstract: IDT723634 IDT723644
Contextual Info: CMOS SyncBiFIFO with Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 Integrated Device Technology, Inc. IDT723624 IDT723634 IDT723644 • Port B bus sizing of 36-bits long word , 18-bits (word) and 9-bits (byte) • Big- or Little-Endian format for word and byte bus sizes

Contextual Info: C M O S B u s -M a tc h in g Sy n c FlF O 256 x 36, 512 x 36, 1,024 x 36 P R E L IM IN A R Y ID T 72 3 62 3 ID T 72 3 63 3 ID T 72 3 64 3 NOTE: There is an errata notice on the fast page and the corrections have been incorporated into this docum ent. FEATURES:

Contextual Info: Integrated Devile Technology, lie. CMOS TRIPLE BUS SyncFIFOT WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 FEATURES: • Two independent FIFOs 64 X 36 storage capacity each buffer data between bidirectional 36-bit port A and two unidirectional 18/9-bit ports (Port B transmits, Port C