FITBL723 Search Results

SN74ALVCH162601

Contextual Info: SN74ALVCH162601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SC ES 026- JULY 1995 • Member of the Texas Instruments Wldebus Family • EPIC™ Enhanced-Performance Implanted CMOS Submicron Process • UBT™ (Universal Bus Transceiver) Combines D-Type Latches and D-Type

62d18

Abstract: fifo ttl B129 B249 SN74ACT2226 SN74ACT2228
Contextual Info: SN74ACT2226, SN74ACT2228 DUAL 6 4 x 1 AND DUAL 256x1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219A - JUNE 1992-R E V IS E D AUGUST 1993 Dual Independent FIFOs Organized as: - 64 Words by 1 Bit Each - SN74ACT2226 - 256 Words by 1 Bit Each - SN74ACT2228 Free-Running Read and Write Clocks Can

74ACT11657

Contextual Info: _ 74ACT11657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS AUGUST 1992-R EVISED APRIL 1993 Inputs Are TTL-Voltage Compatible DW PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout P A R IT Y [ 1 Center-Pin V c c and GND Pin

Transistor BC 1078

Abstract: TSS400-S1 LCD tlc 771 TSS400CFN-S1 abe 630 K-Line L line BC 557 PNP TRANSISTOR circuits D4071 digital pressure sensor conditional circuit 44-PIN
Contextual Info: TSS400-S1 uPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 -D 407 1, JANUARY 1993 * Onboard Ratiometric Current Source Programmable From 0.15 mA x SV^d/V to 2.4 mA x (SVDD/V) Two Independent Crystal Controlled Timers (32.768 kHz) Internal MOS Oscillator Serves as System

SN54AHC86

Abstract: SN74AHC86
Contextual Info: SN54AHC86, SN74AHC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCLS249A - OCTOBER 1995 - REVISED MARCH 1996 Operating Range 2-V to 5.5-V V qq SN54AHC86 . . . J OR W PACKAGE SN74AHC86 . . . D, DB, N, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted

HAI 7203

Abstract: ACT8847 74ACT8847 SN74 multiplier
Contextual Info: TEXAS INSTR LOGIC SSE D 0^1723 GQÖS7G3 7 SN74ACT8847 64-Bit Floating Point Unit • Meets IEEE Standard for Single- and DoublePrecision Formats • Performs Floating Point and Integer Add, Subtract, Multiply, Divide, Square Root, and Compare • 64-Bit IEEE Divide in 11 Cycles, 64-Bit Square

D3165

Contextual Info: ïA " 74AC11286 9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORTS D316S, AUGUST 1988 - REVISED APRIL 1933_ logic symbolt PARITY I/O PARITY ERROR t This symbol is In accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Contextual Info: SN54LVT18646, SN54LVT182646, SN74LVT18646, SN74LVT182646 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS SCBS311A - MARCH 1994 - REVISED JULY 1994 Members of the Texas Instruments SCOPE Family of Testability Products Compatible With the IEEE Standard

SN74ACT7803

Abstract: SN74ACT7805 SN74ACT7813
Contextual Info: SN74ACT7805 256 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS201 - MARCH 1991 - R E V IS E D APRIL 1992 D LPACKAGE TOP VIEW • Member of the Texas Instruments Widebus7" Family • Free-Running Read and Write Clocks Can Be Asynchronous or Coincident • Read and Write Operations Synchronized

CMOS Texas Instruments Incorporated

Abstract: SN74LVC843A
Contextual Info: SN74LVC843A 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS308C - MARCH 1993 - REVISED JANUARY 1997 EPIC Enhanced-Performance Implanted CMOS Submicron Process DB, DW, OR PW PACKAGE (TOP VIEW) Typical V q lp (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C

Contextual Info: SN54F74, SN74F74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET S D F S 0 4 6 A - MARCH 1 9 8 7 - R EVISED O CTO BER 1993 Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic

Contextual Info: 74ACT11153 DUAL 1 OF 4 DATA SELECTOR/MULTIPLEXER S C A S 1 1 8 A -D 3 5 8 3 , JUNE 1990 - R EVISED APRIL 1993 I * Inputs Are TTL-Voltage Compatible • I * Permits Multiplexing From N Lines to One Line I * Performs Parallel-to-Serial Conversion ! * Strobe Enable Line Provided for

31B8

Abstract: 74ACT16470 54AC16470 74AC16470 BS5303 32B4 TI0246 TI0246-D3569 AC16470
Contextual Info: bte: J> TEXAS INSTR L O G I C 0^1723 I 00=10327 ö • T I I 3 54AC16470, 54ACT16470 74AC16470, 74ACT16470 16-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T -5 2 r5 ( TI0248— D3569, JU N E 1990 54AC16470, 54ACT16470 . W D P A C K A G E 74AC16470, 74ACT16470 . D L P A C K A G E

Contextual Info: SN54ALS240A, SN54AS240A, SN74ALS240A, SN74AS240A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SDAS214C - DECEMBER 1982 - REVISED AUGUST 1995 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers SN54ALS240A, SN54AS240A . . . J PACKAGE SN74ALS240A, SN74AS240A . . . DW OR N PACKAGE

Contextual Info: SN74ALS990 8-BIT D-TYPE TRANSPARENT READ-BACK LATCH SD AS027B - APRIL 1984 - R EVISED JANUARY 1995 DW OR N PACKAGE TOP VIEW • 3-State 1/0-Type Read-Back Inputs • Bus-Structured Pinout • True Logic Outputs OERB [ 1 1D [ 2 • Package Options Include Plastic

10E2

Abstract: 20E2 SN54ABT16825 SN74ABT16825
Contextual Info: SN54ABT16825, SN74ABT16825 18-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS S C 8 S 2 1 8 A -J U N E 1 9 9 2 - REVISED JULY 1994 Members of the Texas Instruments Wldebus Family State-of-the-Art EPIC-UB™ BiCMOS Design Significantly Reduces Power Dissipation

SN74ALVCH16373

Contextual Info: SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS S C ES020-JULY 1995 DGQ OR DL PACKAGE TOP VIEW Member of the Texas Instruments Wldebus Family EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per

SN74AHCT04

Contextual Info: SN74AHCT04 HEX INVERTER SCLS232A - OCTO BER 1995 - RE VISED FEBRUARY 1996 D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process High Latch-Up Immunity Exceeds 300 mA Per JEDEC Standard JESD-17

SN74AHCT540

Contextual Info: SN74AHCT540 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCLS268 - DECEMBER 1995 DB, DW, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Package Options Include Plastic Small-Outline (DW). Shrink Small-Outline