A1619A

Abstract: b1241
Contextual Info: SN54ABT32318, SN74ABT32318 18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS SCBS180A-JUNE 1 9 9 2 - REVISED JULY 1994 Members of the Texas Instruments Wldebus+ Family State-of-the-Art EPIC-IlB™ BICMOS Design Significantly Reduces Power Dissipation Typical V q l p Output Ground Bounce

AS09

Abstract: AS639 SN74ALS638A SN74ALS639A SN74AS638A SN74AS639 phl1035
Contextual Info: SN74ALS638A, SN74ALS639A, SN74AS638A, SN74AS639 OCTAL BUS TRANSCEIVERS D2661, DECEMBER 1983 - REVISED MARCH 1987 • Bidirectional But Transceivers in HighDensity 20-Pin Packages SN 74ALS', SN 74 A S '. . . DW OR N PACKAGE TOP VIEW • Choica of Trua or Inverting Logic

ACT7804-20

Abstract: SN74ACT7804 SN74ACT7806 SN74ACT7814
Contextual Info: SN74ACT7804 512x18 STROBED FIRST-IN, FIRST-OUT MEMORY S C A S 2 0 4 A -A P R IL 1992 - REVISED S E P TEM B E R 1995 Member of the Texas Instruments Widebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 512 Words by 18 Bits Low-Power Advanced CMOS Technology

SN54ABT18502

Abstract: H TR 1A60 texas instruments 486 TR 1A60
Contextual Info: SN54ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS109C - AU G U S T 1992 - RE V IS E D AU G U S T 1994 SCOPE Instruction Set - IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ - Parallel-Signature Analysis at Inputs With

Contextual Info: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D 2957, JULY 1987 - R EVISED APRIL 1993 * Flow-Through Architecture Optimizes PCB Layout 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Center-Pin Vcc and GND Configurations

SN74AHCT573

Contextual Info: SN74AHCT573 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS S C L S 2 4 3 B -O C T O B E R 1995 - REVISED JANUARY 1998 OE [ 1D [ 2D [ 3D [ 4D[ 5D[ 6D[ 7D[ 8D[ GND [ description ' u 2 20 1 Vcc 19 ] 1Q 3 18 ] 2Q 4 17 ] 3Q 5 16 ] 4 Q 6 15 j 5Q 7 14 ] 6 Q

HAI 7203

Abstract: ACT8847 74ACT8847 SN74 multiplier
Contextual Info: TEXAS INSTR LOGIC SSE D 0^1723 GQÖS7G3 7 SN74ACT8847 64-Bit Floating Point Unit • Meets IEEE Standard for Single- and DoublePrecision Formats • Performs Floating Point and Integer Add, Subtract, Multiply, Divide, Square Root, and Compare • 64-Bit IEEE Divide in 11 Cycles, 64-Bit Square

Contextual Info: SN74ALS229B 16x5 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORIES D3486, MARCH 1990 Independent Asychronous Inputs and Outputs DW OR N PACKAGE TOP VIEW — U OE[ 1 F U L L -2 [ 2 FU LL[ 3 16 Words by 5 Bits Each Data Rates From 0 to 40 MHz Fall-Through Time . . . 14 ns typ

SN54ABTH182652A

Abstract: SN54ABTH18652A SN74ABTH182652A SN74ABTH18652A
Contextual Info: SN54ABTH18652A, SN54ABTH182652A, SN74ABTH18652A, SN74ABTH182652A SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS _ SCBS167A-AUGUST 1 9 9 3 - REVISED AUGUST 1994 Members of the Texas Instruments SCOPE Family of Testability Products

74ALS533

Abstract: 74AS533
Contextual Info: TEXAS INSTR LOGIC a^biTai Daa3sfis s 2SE D SN54ALS533, SNS4ASS33, SN74ALS533, SN74AS533 OCTAL D TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS D266T, APHIL 1982 - REVISED MAY 1986 SN 54ALS533. SN 54ASS33 . . . J PACKAGE S N 74A LS533, SN 74AS533 . . . DW OR N PACKAGE

SN74ALVCH16901

Contextual Info: SN74ALVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES01D-JULY 1995 • Member of the Texas Instruments Wldebus+ Family • EPIC™ Enhanced-Performance Implanted CMOS Submicron Process • UBT™ (Universal Bus Transceiver)

SN54HCU04

Abstract: SN74HCU04 3 phase inverters circuit diagram
Contextual Info: SN54HCU04, SN74HCU04 HEX INVERTERS SCLS079A - MARCH 1984 - REVISED JANUARY 1996 Unbuffered Outputs SN54HCU04. . . J OR W PACKAGE SN74HCU04 . . . D OR N PACKAGE TOP VIEW Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and

3 phase waveform generator

Abstract: CDC2536
Contextual Info: CDC2536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCAS377 - APRIL 1994 DL PACKAGE TOP VIEW 1 2 3 4 5 6 8 9 10 11 12 13 14 u 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Distributed Vcc and Ground Pins Reduce Switching Noise Packaged in Platic 28-Pin Shrink Small

Contextual Info: SN54ALS576B, SN54AS576 SN74ALS576B, SN74ALS577A, SN74AS576 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS065B - DECEMBER 1982 - REVISED JANUARY 1995 • 3-State Buffer-Type Inverting Outputs Drive Bus Lines Directly • Bus-Structured Pinout

LVTH16373

Abstract: SN54LVTH16373 SN74LVTH16373
Contextual Info: SN54LVTH16373, SN74LVTH16373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SC B S 144G - MAY 1 9 9 2 - REVISED DECEMBER 1996 • State-of-the-Art Advanced BiCMOS Technology ABT Design for 3.3-V Operation and Low-Static Power Dissipation

BCT8244A

Abstract: SN54BCT8244A SN74BCT8244A
Contextual Info: SN54BCT8244A, SN74BCT8244A SCAN TEST DEVICES WITH OCTAL BUFFERS SCBS042D - FEBRUARY 1990 - REVISED APRIL 1994 SN 54BCT8244A . . . JT PACKAGE SN 74BCT8244A . . . DW OR NT PACKAGE TOP VIEW Members of the Texas Instruments SCOPE Family of Testability Products

Contextual Info: SN54LVT18652, SN54LVT182652, SN74LVT18652, SN74LVT182652 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS SCBS312A- MARCH 1 9 9 4 - REVISED JULY 1994 Members of the Texas Instruments SCOPE Family of Testability Products Compatible With the IEEE Standard

SN77702

Contextual Info: SN77702 TRINARY ENCODER SCTS036A - APRIL 1992 - REVISED MAY 1996 • Converts Trinary Switch Inputs Into Digital Pulse-Width Code Stream • Compatible With SN77701 Decoder • • More Than 19000 Possible Codes Low Power Consumption for Battery Operation

D3103

Contextual Info: 54AC11238, 74AC11238 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D3103, APRIL 1988 - REVISED APRIL 1993 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems 54AC11238 . . . J PACKAGE 74AC11238. . . D OR N PACKAGE {TOP VIEW Noninverting Version of 'AC11138

LVT125

Abstract: SN54LVT125 SN74LVT125 J914
Contextual Info: SN54LVT125, SN74LVT125 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS _ . S C B S 1 3 3 B - MAY 1992 -R E V IS E D FEBRUARY 1994 • State-of-the-Art Advanced BiCMOS Technology ABT Design for 3.3-V Operation and Low-Static Power Dissipation

AHCT16373

Abstract: SN54AHCT16373 SN74AHCT16373
Contextual Info: SN54AHCT16373, SN74AHCT16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS336A - MARCH 1996 - REVISED NOVEMBER 1996 Members of the Texas Instruments Widebus Family SN54AHCT16373 . . . WD PACKAGE SN74AHCT16373 . . . DGG OR DL PACKAGE TOP VIEW

LVT574

Abstract: SN54LVT574 SN74LVT574
Contextual Info: SN54LVT574, SN74LVT574 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS139B - MAY 1992 - REVISED FEBRUARY 1994 State-of-the-Art Advanced BiCMOS Technology ABT Design for 3.3-V Operation and Low Static Power Dissipation Support Mixed-Mode Signal Operation (5-V

U161A

Contextual Info: TEXAS INSTR LOGIC SSE D ÒTbl723 0GÖ31QÖ S SN 54A LS157, SN 54A LS 158, S N 5 4A S 157 , S N 54A S 158 S N 74A LS 157, S N 74A LS 158, S N 74A S 157, S N 74A S 158 QUADRUPLE 1 OF 2 DATA SELECTORSfMULTIPLEXERS D 2 66 1, A P R IL 1 9 8 2 - R E V IS E O M A Y 19 86

IEEE1194

Abstract: SN74GTL16921
Contextual Info: SN74GTL16921 20-BIT FLIP-FLOP WITH GTL I/O LEVELS S C B S 3 1 3 -J U L Y 1 9 9 3 - R E V IS E D MARCH 1994 EPIC-TIB Enhanced-Performance Implanted CMOS Submicron Process Members of the Texas Instruments Widebus™ Family Provides GTL Signals Levels on Both