FREEZE ALARM Search Results

Buzzer 12v

Abstract: Buzzer 12v ac 5. buzzer alarm Buzzer 12v to 24v dc 1.2v to 24v circuit Buzzer 12v quad video screen
Contextual Info: 4 CHANNEL DUPLEX B/W & COLOUR MULTIPLEXER FEATURE : 1. High resolution 1024 x 512 2. Duplex operation 3. Auto and user adjustable VCR synchronization 4. Bounce free sequencing 5. FREEZE function in live and playback mode 6. On screen menu setup 7. TIME and DATE generator

SPRING Controller TYCO

Abstract: relay 28.12 855010 Heat Trace Triac soft start MONI-RTD-200 "SPRING Controller" TYCO 8550101
Contextual Info: 910 Series Single-point heat-trace controller Product overview The DigiTrace 910 is a compact, full-featured microprocessor-based single-point heat trace controller. The 910 provides control and monitoring of electrical heat-tracing circuits for both freeze protection and temperature

AN348

Abstract: DS2153 DS2153Q DS2154 DS2154L RC32 TC32
Contextual Info: Maxim > App Notes > TELECOM Keywords: single chip transceivers, SCTs, difference of DS2154 and DS2153, DS0 monitor, per channel loopback, hardware based signaling, signaling freeze Feb 21, 2002 APPLICATION NOTE 348 DS2154L vs. DS2153Q Abstract: This application note highlights the differences between the DS2154L and the DS2153Q E1 single chip

Contextual Info: ISO-CMOS ST-BUSTM Family MT8976 T1/ESF Framer Circuit Data Sheet Features July 2005 • D3/D4 or ESF framing and SLC-96 compatible • 2 frame elastic buffer with 32 µsec jitter buffer • Insertion and detection of A, B,C,D bits. Signalling freeze, optional debounce

MT8976AE

Abstract: phase status word MT8976 MT8976AP MT8976APR MT8977 MT8979 MT8976AP1
Contextual Info: ISO-CMOS ST-BUSTM Family MT8976 T1/ESF Framer Circuit Data Sheet Features September 2005 • D3/D4 or ESF framing and SLC-96 compatible • 2 frame elastic buffer with 32 µsec jitter buffer • Insertion and detection of A, B,C,D bits. Signalling freeze, optional debounce

Contextual Info: ISO-CMOS ST-BUSTM Family MT8976 T1/ESF Framer Circuit Data Sheet Features September 2005 • D3/D4 or ESF framing and SLC-96 compatible • 2 frame elastic buffer with 32 µsec jitter buffer • Insertion and detection of A, B,C,D bits. Signalling freeze, optional debounce

DS2186

Abstract: DS2187 DS2176 DS2176N DS2176Q DS2180A 193s
Contextual Info: DS2176 DS2176 T1 Receive Buffer PIN ASSIGNMENT • Synchronizes loop–timed and system–timed T1 data 1 24 VDD 2 23 SCLKSEL RCLK 3 22 SYSCLK RSER 4 21 SSER A 5 20 SLIP B 6 19 SBIT8 C 7 18 SMSYNC D 8 17 SIGFRZ SCHCLK 9 16 SFSYNC SM0 10 15 ALN SM1 11 14 FMS

Contextual Info: r jA l 1 AQ sEsaicsDMDtiCfoii DS2176 T1 Receive Buffer PIN ASSIGNMENT FEATURES Synchronizes loop-timed and system-timed T1 data streams Two-frame buffer depth; slips occur on frame boundaries Output indicates when slip occurs Buffer may be recentered externally

DS2176

Abstract: DS2176N DS2176Q DS2180A
Contextual Info: DS2176 T1 Receive Buffer www.dalsemi.com PIN ASSIGNMENT § § § § § § § § § § § § § Synchronizes loop–timed and system–timed T1 data streams Two–frame buffer depth; slips occur on frame boundaries Output indicates when slip occurs Buffer may be recentered externally

PVD100

Contextual Info: DS2176 T1 Receive Buffer www.dalsemi.com PIN ASSIGNMENT SIGH RMSYN RCLK RSER A B C D SCHCLK SM0 SM1 1 2 3 4 5 6 7 8 9 10 11 12 VSS VDD SCKLSEL SYCLK SSER SLIP SBIT8 SMSYNC SIGFRZ SFSYNC ALN FMS 24 23 22 21 20 19 18 17 16 15 14 13 S/P 24-PIN 300 MIL DIP A B

Contextual Info: DALLAS DS2176 T 1 Receive Buffer s e m ic o n d u c to r FEATURES PIN ASSIGNMENT • Synchronizes lo o p -tim e d and syste m -tim ed T1 data stream s C 1 24 □ VDD RMSYNC C 2 23 □ SCLKSEL RCLK C 3 22 □ SYSCLK RSER C 4 21 □ SSER s ig h • T w o-fram e buffer depth; slips occur on frame bound­

Contextual Info: DS2176 DALLAS SEMICONDUCTOR DS2176 T 1 Receive Buffer PIN ASSIGNMENT FEATURES • Synchronizes loop-timed and system-timed T1 data streams U ghC 1 24 RMSYNCC 2 23 • Two-frame buffer depth; slips occur on frame bound­ aries • Output indicates when slip occurs

Contextual Info: DALLAS SEMICONDUCTOR DS2176 T1 Receive Buffer FEATURES PIN ASSIGNMENT • Synchronizes loop-timed and system-timed T1 data streams s ìg h C 1 24 H VDD RMSYNC C 2 • Two-frame buffer depth; slips occur on frame bound­ aries • Output indicates when slip occurs

Contextual Info: DALLAS SEMICONDUCTOR DS2176 T 1 Receive Buffer FEATURES PIN ASSIGNMENT • Synchronizes loop-timed and system-timed T 1 data streams s ig h C 1 24 □ VDD C 2 23 3 SCLKSEL rclkC 3 RMSYNC • Two-frame buffer depth; slips occur on frame bound­ aries 22 □ SYSCLK

193-EF

Abstract: 07039
Contextual Info: DALLAS SEMICONDUCTOR DS2176 T1 Receive Buffer FEATURES PIN ASSIGNMENT Synchronizes loop-tim ed and syste m -tim ed T1 data streams E 1 24 □ VDD RMSYNC □ 2 23 □ SCLKSEL RCLK □ 3 22 □ SYSCLK RSER □ 4 21 □ SSER A □ 5 20 □ SLIP B C 6 19 □ SBIT8

880 Leitch product guide

Abstract: Leitch Video 2003 product guide PS-8102 adc8032 Leitch Video FR-6800 leitch ADC-8032A-S FR6800 cross reference ADL-8520
Contextual Info: Ross Video Limited ADC-8032A ADC-8032A-S Analog Composite to SDI Decoder User Manual Ross Part Number: 8032AD-004 Issue: 04 ADC-8032A • Analog Composite to SDI Decoder User Manual • • • • Ross Part Number: 8032AD-004 Document Issue: 04 Printing Date: November 12, 2003. Printed in Canada.

Contextual Info: Standard Product August 1992 LXP2176 T 1 R eceive Buffer Features General Oescrtpiion The LXP2176 is one of a family of Level One T1 interface solutions and is compatible with the LXT300/301 Trans­ ceiver, the LXP2180A Framer/Formatter, and the LXP600/ 601 Clock Rate Adapter. The LXP2176 is a low-power

DS2176

Abstract: DS2176IND DS2176Q DS2180A
Contextual Info: DA L L A S S E M I C O N D U C T O R C O R P CHE D | Et.14130 GODSflflS 4 | Dallas Sem iconductor T-~i£-n-3i T 1 R e c e i ve B u ffe r FEATURES Synchronizes loop-timed and systemtimed T1 data streams Two-frame buffer depth; slips occur on frame boundaries

Contextual Info: 7455 HD/SD/ASI/310M Protection Switch The 7455 module is a fail-safe, bypass protection switch for critical digital paths for broadcast or satellite applications. When a fault is detected in the primary input, and the secondary input is verified as good, the switch will activate,

Contextual Info: LXP2176 T 1 Receive Buffer Oenerai Description N a tu re s The LXP2176 is one of a family of Level One T1 interface solutions and is compatible with the LXT300/301 Trans­ ceiver, the LXP2180A Framer/Formatter, and the LXP600/ 601 Clock Rate Adapter. The LXP2176 is a low-power

Contextual Info: DS2176 FEATURES PIN CONNECTIONS • Synchronizes loop-tim ed and systemtim ed T1 data stream s • Two-frame buffer depth; slips occur on fram e boundaries • O utput indicates when slip occurs • B uffer may be recentered externally • Ideal for 1.544 to 2.048 MHz rate con­

ACC Microelectronics Corporation

Abstract: 0-15 minutes timer ACC Microelectronics acc micro 2036 ACC micro "ACC Microelectronics" ACC Microelectronics notebook ACC 2036 acer lcd monitor circuit diagram acc micro 2020
Contextual Info: A C C MICROELECTRONICS 37E D • GQ2001Ô Q00Q3SM □ * A C E Preliminary Information ACC Micro 2020 2020 Power Management Chip The PMC™ 2020 is designed to reduce the total power consumption of a Notebook computer system with an easy-to-use interface. By minimizing power consumption, the 2020 extends the

Contextual Info: Standard Product August 1992 LXP2176 T 1 Receive Buffer T he L X P2176 is one o f a fam ily o f L evel O ne T1 interface solutions and is com patible w ith the LXT300/301 T rans­ • D rop-in replacem ent for th e DS2176 ceiver, the L X P 2 180A Fram er/Form atter, and the L X P600/

CN001

Abstract: CN007 cn004 PFMC-096 PFMC
Contextual Info: COLOR MEMORY BOARD PFMC – XXX 5 PAL version 0 NTSC 5 PAL 032 – 32 pictures 064 – 64 pictures * 096 – 96 pictures (*) 128 – 128 pictures (*) minimum order : 50 pces INSTRUCTION MANUAL 07/05/2011 Table of contents I. Outline. 1. 1) Specifications.