S2180AT1 Search Results

signalling and frame alignment in E1

Abstract: DS2176 DS2176N DS2176Q DS2180A DS2186 DC817 BC619
Contextual Info: DS 2176 DALLAS DS2176 T 1 Receive Buffer s e m ic o n d u c to r PIN ASSIGNMENT FEATURES • Synchronizes loop -tim e d and system -tim e d T1 data stream s 1 24 □ VDD RMSYNC C 2 s ig h C 23 □ SCLKSEL • T w o -fra m e buffer depth; slips occur on frame bound­

S2186

Contextual Info: D S 2186 DALLAS SEMICONDUCTOR FEATURES DS2186 Transmit Line Interface PIN ASSIGNMENT • Line interface for T1 1.544 MHz and C EPT (2.048 MHz) prim ary rate networks TAIS Q • O n -ch ip transm it LBO (line build out) and line drivers elim inate external components

Contextual Info: DS2181A DA LLAS s e m ic o n d u c to r FEATURES DS2181A C E P T Primary Rate Transceiver PIN ASSIGNMENT • S in g le -ch ip primary rate transceiver m eets CCITT standards G.704, G.706 and G.732 • Supports new C RC4-based fram ing standards and CAS and CCS signalling standards

193-EF

Abstract: 07039
Contextual Info: DALLAS SEMICONDUCTOR DS2176 T1 Receive Buffer FEATURES PIN ASSIGNMENT Synchronizes loop-tim ed and syste m -tim ed T1 data streams E 1 24 □ VDD RMSYNC □ 2 23 □ SCLKSEL RCLK □ 3 22 □ SYSCLK RSER □ 4 21 □ SSER A □ 5 20 □ SLIP B C 6 19 □ SBIT8