FSEA30 Search Results

AD9755

Abstract: AD9755AST AD9755ASTRL AD9755-EB P1B10 MHz VCO C0225
Contextual Info: FEATURES 14-Bit Dual Muxed Port DAC 300 MSPS Output Update Rate Excellent SFDR and IMD Performance SFDR to Nyquist @ 25 MHz Output: 71 dB Internal Clock Doubling PLL Differential or Single-Ended Clock Input On-Chip 1.2 V Reference Single 3.3 V Supply Operation

AD9753

Abstract: AD9753AST AD9753ASTRL AD9753-EB P1B10 Opt pam circuit
Contextual Info: 12-Bit, 300 MSPS High Speed TxDAC+ D/A Converter AD9753* APPLICATIONS Communications: LMDS, LMCS, MMDS Base Stations Digital Synthesis QAM and OFDM GENERAL DESCRIPTION The AD9753 is a dual, muxed port, ultrahigh speed, singlechannel, 12-bit CMOS DAC. It integrates a high quality 12-bit

AD9763

Abstract: AD9763AST AD9763-EB AWG2021
Contextual Info: a FEATURES 10-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR to Nyquist @ 5 mHz Output: 75 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation

48-PIN

Abstract: AD9709 AD9709AST AD9709-EB AWG2021
Contextual Info: a FEATURES 8-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR to Nyquist @ 5 MHz Output = 66 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation

agilent 8112a

Abstract: ad8369 AD6645 AD8369ARU AD8369ARU-REEL7 AD8369EVAL ETC1-1-13 hexadecimal to Binary
Contextual Info: 45 dB Digitally Controlled VGA LF to 600 MHz AD8369* FEATURES Digitally Controlled Variable Gain in 3 dB Steps –5 dB to +40 dB RL = 1 k⍀ –10 dB to +35 dB (RL = 200 ⍀) Less than 0.2 dB Flatness over a +20 MHz Bandwidth up to 380 MHz 4-Bit Parallel or 3-Wire Serial Interface

Contextual Info: ANALOG DEVICES FEATURES High Accuracy 1 Degree rms Quadrature Error @ 1.9 GHz 0.2 dB l/Q Am plitude Balance @ 1.9 GHz Broad Frequency Range: 0.8 G H z-2.5 GHz Sideband Suppression: -4 6 dBc @ 0.8 GHz Sideband Suppression: -3 6 dBc @ 1.9 GHz M odulation Bandwidth: D C-70 MHz

SMA200UP

Abstract: AD9767-EBZ
Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM 10-/12-/14-bit dual transmit digital-to-analog converters DACs 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc Excellent gain and offset matching: 0.1% Fully independent or single-resistor gain control

BY200

Abstract: LTE filter 6235A adl5380 ADL5380ACPZ IP1dB TC1-1-13 E3X-SD11 AN-772 5 channel RF transmitter and Receiver circuit
Contextual Info: 400 MHz to 6 GHz Quadrature Demodulator ADL5380 FEATURES FUNCTIONAL BLOCK DIAGRAM ENBL ADJ ADL5380 IHI BIAS ILO LOIP RFIN V2I QUADRATURE PHASE SPLITTER RFIP LOIN QHI QLO 07585-001 Operating RF and LO frequency: 400 MHz to 6 GHz Input IP3 30 dBm @ 900 MHz 28 dBm @1900 MHz

E4405B

Abstract: 8648c agilent signal generator jammer gsm 143FH jammer circuit TD-SCDMA 2010M MAX2306 MAX2308
Contextual Info: WIRELESS, RF, AND CABLE Mar 26, 2003 TD-SCDMA Reference Design V1.0 This application note presents Maxim's TD-SCDMA reference design V1.0. TDSCDMA is the Chinese Third Generation 3G standard. China's government has allocated 3 frequency bands: 1880~1920MHz, 2010~2025MHz, and 2300~2400MHz.

SMA200UP

Abstract: db3p1 INP32 ad8055 T1-1TCUP AD9763 AD9765 AD9767
Contextual Info: 10-/12-/14-Bit, 125 MSPS Dual TxDAC+ Digital-to-Analog Converters AD9763/AD9765/AD9767 FEATURES FUNCTIONAL BLOCK DIAGRAM 10-/12-/14-bit dual transmit digital-to-analog converters DACs 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc

Contextual Info: 1000 MHz to 3100 MHz Rx Mixer with Integrated Fractional-N PLL and VCO ADRF6602 Data Sheet FEATURES The PLL can support input reference frequencies from 12 MHz to 160 MHz. The PFD output controls a charge pump whose output drives an off-chip loop filter. Rx mixer with integrated fractional-N PLL

Contextual Info: 400 MHz to 6 GHz Quadrature Demodulator ADL5380 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM ENBL ADJ ADL5380 IHI BIAS ILO LOIP RFIN V2I QUADRATURE PHASE SPLITTER RFIP LOIN QHI QLO 07585-001 Operating RF and LO frequency: 400 MHz to 6 GHz Input IP3 30 dBm @ 900 MHz

db3x

Abstract: AD9740 AD9740ACP AD9740ACPRL7 AD9740AR AD9740ARRL AD9740ARU AD9740ARURL7 AD9740-EB
Contextual Info: 10-Bit, 165 MSPS TxDAC D/A Converters AD9740* FEATURES High Performance Member of Pin Compatible TxDAC Product Family Excellent Spurious-Free Dynamic Range Performance SNR @ 5 MHz Output, 125 MSPS: 65 dB Twos Complement or Straight Binary Data Format Differential Current Outputs: 2 mA to 20 mA

SLOA020

Abstract: FSEA30 THS4011 THS4021 SLOA017
Contextual Info: Amplifiers: Op Amps Texas Instruments Incorporated Using a decompensated op amp for improved performance By Jim Karki Systems Specialist, High-Speed Amplifiers Introduction Figure 1. Open-loop gain and phase—THS4011 and THS4021 If your application requires

LM 3842 Circuit diagram

Abstract: describe LM 3842 la 3842 modo woo sung transformer AD9772 AD9772AST AD9772EB DB10
Contextual Info: ANALOG ► D E V IC E S FEATURES Single 2.7 V to 3.6 V Supply 14-Bit DAC Resolution and Input Data W idth 150 MSPS Input Data Rate 63.3 MHz Reconstruction Passband @ 150 MSPS 75 dBc SFDR @ 25 MHz 2 x Interpolation Filter w ith High or Low Pass Response 73 dB Im age Rejection w ith 0.005 dB Passband Ripple

GRP1555C1H330J

Abstract: GRP1555C1H150J MQW1 CAP 0402 GRP1555C1H120J VC-2R8A50-2139 grp155r71h222k MQE95 MQK301-1528 MQT1C1A897M
Contextual Info: 19-3368; Rev 0; 7/04 MAX2560/MAX2566/MAX2572 Evaluation Kits Features ♦ On-Board PCS and Cellular VCOs ♦ WCDMA, GSM900, DCS1800, GSM1900 Modes MAX2566/MAX2572 EV Kits ♦ 50Ω SMA Connectors on All RF and Baseband Ports ♦ Low-Power Shutdown Mode ♦ EV-Kit Control Software Available at

schematic hp dv7

Abstract: hp dv6 schematic hp dv6 hp dv5 schematic hp dv4 DB15 MALE TO DB9 FEMALE PAB1 schematic hp dv3 hp dv7 schematic pll ADRF6601
Contextual Info: 2100 MHz to 2600 MHz Rx Mixer with Integrated Fractional-N PLL and VCO ADRF6603 The PLL can support input reference frequencies from 12 MHz to 160 MHz. The PFD output controls a charge pump whose output drives an off-chip loop filter. FEATURES Rx mixer with integrated fractional-N PLL

6235A

Abstract: ADL5382 HP87405 AN-772 ETC1-1-13 SMT03 8508A
Contextual Info: 700 MHz to 2.7 GHz Quadrature Demodulator ADL5382 FEATURES FUNCTIONAL BLOCK DIAGRAM CMRF CMRF RFIP RFIN CMRF VPX 23 24 22 21 20 19 VPA 1 ADL5382 18 VPB COM 2 BIAS GEN 17 VPB BIAS 3 16 QHI 0° 90° 15 QLO VPL 4 VPL 5 14 IHI VPL 6 13 ILO 7 CML 8 9 10 LOIP LOIN CML

DVB-t receiver schematic diagram

Abstract: MURATA GRM15 -V2 dvbt active antenna schematic smd L35 MMCX-S50 MOSFET C65 DVB-T Schematic 4MHz CRYSTAL NDK at41 SMD l35 Transistor C86 SOT323
Contextual Info: Published by Infineon Technologies AG 81726 München, Germany Infineon Technologies AG 2007. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics “Beschaffenheitsgarantie” . With respect to any examples or hints given herein, any

AD9744

Contextual Info: 14-Bit, 210 MSPS TxDAC D/A Converter AD9744 Data Sheet FEATURES APPLICATIONS High performance member of pin-compatible TxDAC product family Excellent spurious-free dynamic range performance SFDR to Nyquist 83 dBc at 5 MHz output 80 dBc at 10 MHz output 73 dBc at 20 MHz output

A10007

Abstract: A6458
Contextual Info: 300 MHz to 2500 MHz Rx Mixer with Integrated Fractional-N PLL and VCO ADRF6601 Data Sheet FEATURES The PLL can support input reference frequencies from 12 MHz to 160 MHz. The PFD output controls a charge pump whose output drives an off-chip loop filter. Rx mixer with integrated fractional-N PLL

cdma QPSK modulation Walsh pilot

Abstract: HP34970A Voltage to Current Converters HP8648C HP8593E AD8346 AD9761 ETC1-1-13 AD8346 ETC1-1-13 AFG2020
Contextual Info: 0.8 GHz to 2.5 GHz Quadrature Modulator AD8346 High accuracy 1 degree rms quadrature error @ 1.9 GHz 0.2 dB I/Q amplitude balance @ 1.9 GHz Broad frequency range: 0.8 GHz to 2.5 GHz Sideband suppression: −46 dBc @ 0.8 GHz Sideband suppression: −36 dBc @ 1.9 GHz

A10007

Contextual Info: 750 MHz to 1160 MHz Rx Mixer with Integrated Fractional-N PLL and VCO ADRF6601 FEATURES The PLL can support input reference frequencies from 12 MHz to 160 MHz. The PFD output controls a charge pump whose output drives an off-chip loop filter. Rx mixer with integrated fractional-N PLL

Contextual Info: 12-Bit, 210 MSPS TxDAC D/A Converter AD9742 FEATURES APPLICATIONS High performance member of pin-compatible TxDAC product family Excellent spurious-free dynamic range performance SNR @ 5 MHz output, 125 MSPS: 70 dB Twos complement or straight binary data format